After trench etching but before formation of a gate insulating film, a 15-minute to 60-minute heat treatment under a mixed gas atmosphere containing nitric oxide gas and nitrogen gas at a temperature from 1200 degrees C. to 1350 degrees C. and a 30-minute to 75-minute heat treatment under a nitrogen gas atmosphere held at the temperature of the 15-minute to 60-minute heat treatment are successively performed, oxidizing etching damage of inner walls of trenches. The total treatment time of the heat treatments includes a total time of at least 90 minutes when the temperature is a predetermined maximum temperature. The oxide layer of the trench inner walls is removed, exposing a clean face. Emission intensity of band edge emission for SiC obtained by CL analysis of surface areas of the inner walls of the trenches is at least equal to the emission intensity of the band edge emission for SiC obtained by the CL analysis of a surface free of dry etching.

A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×10.sup.22 cm.sup.−3 or more, a SiO.sub.2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO.sub.2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO.sub.2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO.sub.2 layer and that has a carbon density of 1.0×10.sup.19 cm.sup.−3 or less.

A method of manufacturing a semiconductor integrated circuit includes forming a body region having a second conductivity type in an upper portion of a support layer having a first conductivity type and forming a well region having a second conductivity type in an upper portion of the support layer. An output side buried layer is formed inside the body region and a circuit side buried layer is formed inside the well region. A trench is dug to penetrate through the body region and a control electrode structure is buried in the gate trench. First and second terminal regions are formed on the well region and an output terminal region is formed on the body region. An output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.

In a semiconductor device, a semiconductor element includes a semiconductor substrate, a surface electrode and a protective film. The semiconductor substrate has an active region and an outer peripheral region. The surface electrode includes a base electrode disposed on a front surface of the semiconductor substrate and a connection electrode disposed on the base electrode. The protective film covers a peripheral end portion of the base electrode and an outer peripheral edge of the connection electrode. The protective film has an opening to expose the connection electrode so as to enable a solder connection. A boundary between the outer peripheral edge of the connection electrode and the protective film is located at a position corresponding to the outer peripheral region in a plan view.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

Provided in the present disclosure are an IGBT device backside structure and a preparation method therefor, and an IGBT device, the IGBT device backside structure comprising a buffer layer, the buffer layer comprising a first activation efficiency buffer area corresponding to an active area of the IGBT device and a second activation efficiency buffer area corresponding to a terminal area of the IGBT device, the activation efficiency of the first activation efficiency buffer area being less than the activation efficiency of the second activation efficiency buffer area.

A reverse-conducting insulated gate bipolar transistor and a method of manufacturing the same are disclosed. More particularly, the insulated gate bipolar transistor and the method of manufacturing the same are configured to form a cover layer so as to prevent external exposure of an uppermost surface of a first contact in a first cell region, thereby maximally reducing occurrences of contamination during subsequent processing.

In one embodiment, a power semiconductor device may include a semiconductor substrate, wherein the semiconductor substrate comprises an active device region and a junction termination region. The power semiconductor device may also include a polysilicon layer, disposed over the semiconductor substrate. The polysilicon layer may include an active device portion, disposed over the active device region, and defining at least one semiconductor device; and a junction termination portion, disposed over the junction termination region, the junction termination portion defining a ring structure.

A semiconductor device is formed using a semiconductor substrate having a first main surface and a second main surface. A first semiconductor region of a first conductivity type is formed between the first main surface and the second main surface of the semiconductor substrate. A second semiconductor region is formed between the first semiconductor region and the first main surface. The first semiconductor region includes a hydrogen-related donor, and a concentration of the hydrogen-related donor of the first semiconductor region is equal to or larger than an impurity concentration of the first semiconductor region.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.