A method for manufacturing an epitaxial substrate includes the steps of: epitaxially growing a group III nitride semiconductor layer on a substrate; removing the substrate from a growth furnace; irradiating a surface of the group III nitride semiconductor layer with ultraviolet light while exposing the surface to an atmosphere containing oxygen; and measuring a sheet resistance value of the group III nitride semiconductor layer.

A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

A gate electrode includes a main portion formed of a gate electrode material, and a gate electrode barrier layer disposed between the main portion and a barrier layer and formed of a conductive material that prevents the gate electrode material from diffusing into the barrier layer. A surface of the main portion in a region above a first insulating layer faces a periphery without a layer of the conductive material being formed.

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

A method of manufacturing a semiconductor device includes: forming an electron transit layer; forming an electron supply layer; forming a protective film; forming a zinc oxide film; forming a sacrifice layer; forming a first opening and a second opening in the sacrifice layer and the zinc oxide film; forming a third opening connecting to the first opening and a fourth opening connecting to the second opening; forming, by acid treatment using a weakly acidic solution, a first gap in a first portion exposed to the first opening of the zinc oxide film, and a second gap in a second portion exposed to the second opening of the zinc oxide film; forming, after the acid treatment, a source region on a bottom surface of the third opening and a drain region on a bottom surface of the fourth opening; and removing the zinc oxide film.

A semiconductor device includes a plurality of column portions including a semiconductor. The plurality of column portions each includes a source region, a drain region, and a channel formation region including a channel formed between the source region and the drain region. The semiconductor device further includes a gate electrode provided, via an insulating layer, at a side wall of the channel formation region, and also includes a first semiconductor layer provided at a side wall of the drain region. A conductive type of the first semiconductor layer differs from a conductive type of the semiconductor included in the drain region.

According to one embodiment, a semiconductor device includes first, second, third nitride members, first, second, third electrodes, and a first insulating member. The first nitride member includes a first face along a first plane, a second face along the first plane, and a third face. The third face is connected with the first and second faces between the first and second faces. The third face crosses the first plane. The first face overlaps a part of the first nitride member. The second nitride member includes a first nitride region provided at the first face. The third nitride member includes a first nitride portion provided at the second face. The first electrode includes a first connecting portion. The second electrode includes a second connecting portion. The third electrode includes a first electrode portion. The first insulating member includes a first insulating region.

A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, a nitride region, and a first insulating member. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to sixth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The sixth partial region is between the fifth and second partial regions. The second semiconductor region includes first and second semiconductor portions. The second semiconductor portion is in contact with the fifth partial region. The nitride region includes a first nitride portion being in contact with the sixth partial region. The first insulating member includes a first insulating region between the third partial region and the first electrode portion.