A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. A first gate spacer is separated the gate stack from the source/drain contact structure and extends above top surfaces of the gate stack and the source/drain contact structure. An insulating capping layer covers the top surface of the gate stack and extends on the top surface of the first gate spacer. A conductive via structure partially covers the top surface of the insulating capping layer and the top surface of the source/drain contact structure. A first insulating layer surrounds the conductive via structure and partially covers the top surface of the source/drain contact structure.

A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

A semiconductor device includes: an isolation insulating layer; fin structures protruding from the isolation insulating layer; gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate; a first source/drain epitaxial layer and a second source/drain epitaxial layer disposed between two adjacent gate structures; and a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer; a separation isolation region disposed between the first and second conductive contact; and an insulating layer disposed between the separation isolation region and the isolation insulating layer. The separation isolation region is made of a different material than the insulating layer.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

A method for manufacturing a semiconductor device comprising: providing a substrate, wherein a first gate structure corresponding to a dense area transistor and a second gate structure corresponding to an isolated area transistor are formed on the substrate, and the first gate structure is higher than the second gate structure; forming a buffer layer over the second gate structure, wherein the upper surface of the buffer layer is flush with the upper surface of the first gate structure; and removing the top of the first gate structure, and forming a hard mask filling layer on a top area of the first gate structure.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.

A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.