Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

The present disclosure provides a piezoelectric sensor, a pressure detecting device, their manufacturing methods and a detection method. The piezoelectric sensor comprises a thin film transistor located on a substrate and comprising an active layer, and a piezoelectric layer that is in contact with the active layer of the thin film transistor.

A method for forming a gate-all-around structure is provided. The method includes forming a plurality of a first type of semiconductor layers and a plurality of a second type of semiconductor layers alternately stacked over a fin. The first type of semiconductor layers includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has a thickness greater than that of the second semiconductor layer. The method also includes removing the second type of semiconductor layers. In addition, the method includes forming a gate to wrap around the first type of semiconductor layers.

In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.

The present invention discloses a metal oxide (MO) semiconductor, which is obtained by doping a small amount of rare-earth oxide (RO) as a photo-induced carrier transportion center into an indium-containing MO semiconductor to form a (In.sub.2O.sub.3).sub.x(MO).sub.y(RO).sub.z semiconductor material. According to the present invention, a charge transportion center can be formed by utilizing the characteristics that the radius of rare-earth ions is equal to that of indium ions, and 4f orbitals in the rare-earth ions and 5s orbitals of the indium ions, so as to improve the stability under illumination. The present invention further provides a thin-film transistor based on the MO semiconductor and application thereof.

The present invention discloses a metal oxide (MO) semiconductor, which is implemented by respectively doping at least an oxide of rare earth element R and an oxide of rare earth element R′ into an indium-containing MO semiconductor to form an In.sub.xM.sub.yR.sub.nR′.sub.mO.sub.z semiconductor. According to the present invention, the extremely high oxygen bond breaking energy in the oxide of rare earth element R is used to effectively control the carrier concentration in the semiconductor, and a charge transportation center can be formed by using the characteristic that the radius of rare earth ions is equivalent to the radius of indium ions, so that the electrical stability of the semiconductor is improved. The present invention further provides a thin-film transistor based on the MO semiconductor and application thereof.

A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.

A thin film transistor includes an active layer, first and second electrodes, and a third doped pattern. The active layer has a channel region, and a first electrode region and a second electrode region, the first electrode region has a first ion doping concentration, and the second electrode region has a second ion doping concentration. The first electrode and the second electrode are disposed on a side of the active layer in the thickness direction. The first electrode is coupled to the first electrode region, and the second electrode is coupled to the second electrode region. The third doped pattern is disposed between the first electrode and the first electrode region, and in direct contact with the first electrode and the first electrode region. The third doped pattern has a third ion doping concentration, and the third ion doping concentration is different from the first ion doping concentration.

Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.