An improved passivation structure for GaN field effect transistor comprising at least one dielectric layer formed on a top surface of a GaN field effect transistor and a passivation layer formed on a top surface of the dielectric layer. The GaN field effect transistor has a gate electrode comprising a Schottky contact metal layer, at least one diffusion barrier metal layer and a high conductivity metal layer. The passivation layer is made of a low cure temperature Polybenzoxazole (PBO) which can be cured at a low-temperature. Thereby the intermixing of the Schottky contact metal layer and the the diffusion barrier metal layer are prevented.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum V.sub.DD includes: determining an x value in In.sub.xGa.sub.1-xAs according to the BTBT leakage and the maximum V.sub.DD, and forming a channel utilizing In.sub.xGa.sub.1-xA, wherein x is not 0.53.

A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided.