A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

A semiconductor device that is composed of an epitaxial semiconductor material stacked structure that includes a first epitaxial channel for a first junction field effect transistor (JFET) atop a supporting substrate and a second epitaxial channel region for a second junction field effect transistor (JFET). A commonly electrically contacted source/drain region for each of the first JFET and the second JFET is positioned at an interface of the first and second epitaxial channel region. A channel length for each of the first and second is substantially perpendicular to an upper surface of the supporting substrate. An epitaxial semiconductor gate conductor in direct contact with each of said first epitaxial channel region and the second epitaxial channel region.

The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.

A semiconductor device includes: a first-conductivity-type semiconductor substrate serving as a drain layer; a first-conductivity-type epitaxial layer formed on the semiconductor substrate; a first-conductivity-type source layer formed in a surface part of the epitaxial layer; two second-conductivity-type gate layers formed in the surface part of the epitaxial layer so as to sandwich the source layer; a first-conductivity-type channel forming layer formed so as to be sandwiched between the two gate layers, the first-conductivity-type channel forming layer being formed on an inner side of the source layer in the epitaxial layer; and an electrode connected to one of the drain layer, the source layer, and the gate layer. In the channel forming layer, two first-conductivity-type impurity layers each having a substantially predetermined width are formed adjacent to each other in a direction crossing a channel.