A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface.

In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches.

A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

Example implementations include a bandgap voltage device with a first current source operatively coupled to a bandgap input node and a bandgap output node and operable to output a first proportional-to-absolute-temperature (PTAT) current, a current mirror including a first bandgap transistor and a second bandgap transistor, and operatively coupled to the bandgap output node, and a second current source operatively coupled to the current mirror and operable to output a second PTAT current. Example implementations also include a bandgap transistor device with a first P+ layer proximate to a center of a planar surface of a transistor device, a first N+ layer at least partially surrounding the first P+ layer along the planar surface, a second P+ layer at least partially surrounding the first N+ layer along the planar surface, a second N+ layer at least partially surrounding the second P+ layer along the planar surface, and a third P+ layer at least partially surrounding the second N+ layer along the planar surface.

The present application discloses new approaches to providing passive-off protection for a B-TRAN-like device. Even if the control circuitry is inactive, AC coupling uses transient voltage on the external terminals to prevent forward biasing an emitter junction. Preferably the same switches which implement diode-mode and pre-turnoff operation are used as part of the passive-off circuit operation.

A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.

The present disclosure provides a semiconductor device that prevents a resistor component connected in series with a base electrode from the electrostatic damage. A semiconductor device includes, a collector layer, which is a first conductivity type semiconductor, a base layer, which is a second conductivity type semiconductor and connected with the collector layer, an emitter layer, which is the first conductivity type semiconductor and connected with the base layer, a first electrode, electrically connected to the base layer, a first resistor component, connected in series with the first electrode in a conductive path connecting the first electrode and the base layer, a second electrode, electrically connected to the emitter layer and the first resistor component; and a protection component, connected to the first electrode in parallel with the first resistor component, wherein the protection component comprises a pair of diodes formed by a pn junction and by a way of making both ends of the conductive path into a same polarity.

A power semiconductor device is disclosed. In one example, the device comprises: a semiconductor body comprising a drift region, the drift region having dopants of a first conductivity type; an active region having at least one power cell; least partially into the semiconductor body; the at least one power cell being configured to conduct a load current between said terminals and to block a blocking voltage applied between said terminals; an edge that laterally terminates the semiconductor body; and a non-active termination structure arranged in between the edge and the active region. The termination structure comprises: at least one doped semiconductor region implemented in the semiconductor body; a conductor structure, and an ohmic path that electrically couples the conductor structure with an electrical potential of the first load terminal.