A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.

A semiconductor device including: a P-type base region provided; an N-type emitter region provided inside the P-type base region; a P-type collector region that is provided on the surface layer portion of the N-type semiconductor layer and is separated from the P-type base region; a gate insulating film that is provided on the surface of the N-type semiconductor layer, and that contacts the P-type base region and the N-type emitter region; a gate electrode on the gate insulating film; a pillar shaped structure provided inside the N-type semiconductor layer between the P-type base region and the P-type collector region, wherein one end of the pillar shaped structure is connected to an N-type semiconductor that extends to the surface layer portion of the N-type semiconductor layer, and the pillar shaped structure includes an insulator extending in a depth direction of the N-type semiconductor layer.

Provided is a lateral insulated-gate bipolar transistor (LIGBT), comprising a substrate (10), an anode terminal and a cathode terminal on the substrate (10), and a drift region (30) and a gate (61) located between the anode terminal and the cathode terminal. The anode terminal comprises a P-type buried layer (52) on the substrate (10), an N-type buffer region (54) on the P-type buried layer (52), and a P+ collector region (56) on the surface of the N-type buffer region (54). The LIGBT further comprises a trench gate adjacent to the anode terminal, wherein the trench gate penetrates from the surfaces of the N-type buffer region (54) and the P+ collector region (56) to the P-type buried layer (52), and the trench gate comprises an oxidation layer (51) on the inner surface of a trench and polysilicon (53) filled into the oxidation layer.

A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.

A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer and a carrier storage layer over the drift layer; a collector layer on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and the carrier storage layer and reaching the drift layer; a gate electrode on an insulation film in each trench; and an emitter region in a surface portion of the base layer contacting each trench. A thickness of at least a portion of a part of the gate insulation film on a sidewall of each trench on a collector layer side from a peak position, at which the impurity concentration of the carrier storage layer is highest, is thicker than a thickness of another part of the gate insulation film on the sidewall of an opening portion side of the trench from the peak position.

A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

A memtransistor includes a top gate electrode and a bottom gate electrode; a polycrystalline monolayer film formed of an atomically thin material disposed between the top gate electrode and the bottom gate electrode; and source and drain electrodes spatial-apart formed on the polycrystalline monolayer film to define a channel in the polycrystalline monolayer film between the source and drain electrodes. The top gate electrode and the bottom gate electrode are capacitively coupled with the channel.