The disclosure provides a superjunction IGBT (insulated gate bipolar transistor) device, wherein a carrier storage layer of a first conductivity type is provided between a voltage sustaining layer and a base region, and a MISFET (metal-insulator-semiconductor field effect transistor) of a second conductivity type is also integrated in a cell, with at least one gate of the MISFET is connected to the emitter contact thereof. The MISFET is turned off at a low forward conduction voltage, helping to reduce the conduction voltage drop. The MISFET can provide a path for carriers of a second conductivity type and prevent the carrier storage layer from suffering a high electric field when the forward conduction voltage is slightly higher or it is at the forward blocking state, helping to improve the reliability.

A semiconductor device includes: an n-type semiconductor substrate; a p-type base layer formed on a surface of the n-type semiconductor substrate; an n-type emitter layer formed on the p-type base layer, a trench gate penetrating through the p-type base layer and the n-type emitter layer; an n-type carrier stored layer formed between the n-type semiconductor substrate and the p-type base layer and having a higher concentration than that of the n-type semiconductor substrate; and a p-type collector layer formed on a back surface of the n-type semiconductor substrate, wherein with respect to the n-type carrier stored layer, a concentration gradient directing from a position of a peak concentration to the back surface of the n-type semiconductor substrate is larger than a concentration gradient directing from the position of the peak concentration to the p-type base layer, and a proton is implanted in the n-type carrier stored layer as an impurity.

A semiconductor device is provided that includes an insulated gate field effect transistor series connected with a FET having several parallel conductive layers, a substrate of first conductivity type extending under both transistors, and a first layer of a second conductivity type overlies the substrate. Above this first layer are several conductive layers with channels formed by several of the first conductivity type doped epitaxial layers with layers of a first conductivity type on both sides. The uppermost layer of the device may be substantially thicker than the directly underlying parallel conductive layers. The JFET is isolated with deep poly trenches of second conductivity type on the source side. The insulated gate field effect transistor is isolated with deep poly trenches of the first conductivity type on both sides. A further isolated region is isolated with deep poly trenches of the first conductivity type on both sides.

A semiconductor device structure may include a semiconductor device, disposed at least in part in a semiconductor substrate, and a first insulator layer, disposed on a surface of the semiconductor device, and comprising a first contact aperture, disposed within the first insulator layer. The semiconductor device structure may also include a first contact layer, comprising a first electrically conductive material, disposed over the insulator layer, and being in electrical contact with the semiconductor device through the first contact aperture, and a second insulator layer, disposed over the first contact layer, wherein the second insulator layer further includes a second contact aperture, displaced laterally from the first contact aperture, by a first distance. The semiconductor device structure may further include a second contact layer, comprising a second electrically conductive material, disposed over the second insulator layer, and electrically connected to the semiconductor device through the first and second contact aperture.

The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n.sup. type drift region and not penetrating a SiC substrate; an n.sup.+ type side surface diffusion region formed on each side surface of the first trench; an n.sup.+ type bottom diffusion region formed under the n.sup. type drift region and in contact with the n.sup.+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n.sup. type drift region at regular spacings of 0.4 m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.

A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.

A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

An emitter interconnection connecting the emitter of a semiconductor switching element to a negative electrode is different in one or both of length and width from an emitter interconnection connecting the emitter of a semiconductor switching element to the negative electrode. At the time of switching, an induced electromotive force is generated at a gate control wire, or at a gate pattern, or at an emitter wire, by at least one of a current flowing through a positive electrode and a current flowing through the negative electrode, so as to reduce the difference between the emitter potential of the semiconductor switching element and the emitter potential of the semiconductor switching element caused by the difference.

A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

A horizontal vacuum channel transistor is provided. The horizontal transistor includes a substrate, horizontal emitter and collector electrodes formed in a layer of semiconductor material of the substrate, and a horizontal insulated gate located between the emitter and collector electrodes. The emitter electrode includes multiple horizontally-aligned emitter tips connected to a planar common portion, and the collector electrode includes a planar portion. The gate includes multiple horizontally-aligned gate apertures passing through the gate that each correspond to one of the emitter tips of the emitter electrode. The minimum distance between the emitter and collector electrodes is less than about 180 nm. Also provided are a vertical vacuum channel transistor having vertically-stacked emitter and collector electrodes, and methods for fabricating vacuum channel transistors.