Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.

A semiconductor device includes a first switching element; a second switching element; a first metal member; a second metal member; a first terminal that has a potential on a high potential side; a second terminal that has a potential on a low potential side; a third terminal that has a midpoint potential; and a resin part. A first potential part has potential equal to potential of the first terminal. A second potential part has potential equal to potential of the second terminal. A third potential part has potential equal to potential of the third terminal. A first creepage distance between the first potential part and the second potential part is longer than a minimum value of a second creepage distance between the first potential part and the third potential part and a third creepage distance between the second potential part and the third potential part.

A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

A power semiconductor device includes a semiconductor body; a first load terminal at the semiconductor body; and a second load terminal at the semiconductor body. The power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal. The first load terminal has a first side and a second side adjoining the semiconductor body. The first load terminal includes: at the first side, an atomic layer deposition (ALD) layer; at the second side, a base layer including copper; and between the ALD layer and the base layer, a coupling layer that includes copper-silicon-nitride (CuSiN).

Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

An object is to provide a semiconductor device that implements cost reduction as well as determination of withstand voltage characteristics. A semiconductor substrate includes a semiconductor element on the front surface thereof and a back surface electrode on the back surface thereof that controls the operation of the semiconductor element. A first electrode and a second electrode are provided in a terminal region outside an active region in which the semiconductor element is formed. An insulating film is provided between the first electrode and the second electrode. The second electrode is provided on an insulating interlayer film provided on the front surface of the semiconductor substrate. The first electrode is in contact with the front surface of the semiconductor substrate and is provided on the semiconductor substrate closer to an end portion thereof than the second electrode is, and is electrically connected to the back surface electrode.

Provided is a semiconductor device, including at least: a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of an m-axis in the semiconductor layer being the first direction.

A semiconductor device includes: a drift region of a first conductivity type arranged between first and second surfaces of a semiconductor body; a first region of the first conductivity type at the second surface; a second region of a second conductivity type arranged adjacent to the first region at the second surface, the second region including first and second sub-regions, the second sub-region arranged between the first sub-region and the second surface; and a first electrode on the second surface and arranged directly adjacent to the first region and the second sub-region. The first electrode is electrically connected to the drift region by the first region. The first sub-region protrudes, along a first lateral direction, over an interface or a separation region between the second sub-region and the first region. A part of the first region is confined by the first sub-region and the first electrode along a vertical direction.