Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

A method of manufacturing a semiconductor device comprises steps of: forming a semiconductor stack by growing an AlGaN layer or an InAlN layer, an AlN layer, and a GaN layer on a substrate in this order; forming a recess in the semiconductor stack by a dry etching from a surface of the semiconductor stack, the surface being opposite to the substrate; growing a GaN region in the recess; and forming an ohmic electrode on the GaN region; wherein in the forming of the recess, the dry etching is stopped in response to the recess reaching the AlN layer.

A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

A semiconductor structure and a manufacturing method thereof is provided. The semiconductor structure includes a high-resistance silicon substrate and a compound layer located on the high-resistance silicon substrate, by performing a way such as local n-type ion implantation, local n-type ion diffusion, selective region epitaxy growth and the like to the high-resistance silicon substrate, an upper part of the high-resistance silicon substrate is formed into a plurality of local n-type semiconductor regions, p-type semiconductor conductive regions formed in the upper part of the high-resistance silicon substrate due to a diffusion of Al, Ga atoms in the compound layer are eliminated, thereby parasitic capacitance caused by a conductive substrate is greatly reduced, and a resistivity of the high-resistance silicon substrate may be improved under high temperature conditions, and then efficiencies and radio frequency characteristics of a microwave device constituted by the entire semiconductor structure are improved.

The present application provides a method for preparing a p-type semiconductor structure, an enhancement mode device and a method for manufacturing the same. The method for preparing a p-type semiconductor structure includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer, and at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.

The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

A semiconductor device includes a first and a second switching element, a first and a second conductive member, and a capacitor. The first switching element has a first element obverse surface and a first element reverse surface facing away from each other in a first direction. The second switching element has a second element obverse surface and a second element reverse surface facing away from each other in the first direction. The first and second conductive members are spaced apart in a second direction orthogonal to the first direction. The capacitor has a first and a second connection terminal. The first and second switching elements are connected in series, forming a bridge. The first and second connection terminals are electrically connected to opposite ends of the bridge. The capacitor and the first switching element are on the first conductive member, the second switching element on the second conductive member.

The invention relates to a semiconductor component comprising at least one field effect transistor, said transistor comprising at least a back barrier layer, a buried layer arranged on the back barrier layer, a channel layer arranged on the buried layer, a barrier layer arranged on the channel layer, and a gate layer arranged on the barrier layer, wherein the barrier layer comprises Al.sub.zGa.sub.1-zN and wherein the buried layer comprises Al.sub.xGa.sub.1-xN and at least one dopant causing a p-type conductivity, and wherein the gate layer comprises any of GaN and/or Al.sub.uIn.sub.vGa.sub.1-v-uN. A field effect transistor according to the disclosure may be configured to show a gate threshold voltage which is higher than approximately 0.5 V or higher than approximately 1.0 V.

A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.