A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.

A High Electron Mobility Transistor (HEMT) device can include an AlN buffer layer on a substrate and an epi-GaN channel layer on the AlN buffer layer. An AlN barrier layer can be on the Epi-GaN channel layer to provide a channel region in the epi-GaN channel layer. A GaN drain region can be recessed into the epi-GaN channel layer at a first end of the channel region and a GaN source region can be recessed into the epi-GaN channel layer at a second end of the channel region opposite the first end of the channel region. A gate electrode can include a neck portion with a first width that extends a first distance above the AlN barrier layer between the GaN drain region and the GaN source region to a head portion of the gate electrode having a second width that is greater than the first width.

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

Current collapse of a normally-on type dual-gate bidirectional switch is suppressed. Dual-gate bidirectional switch includes first gate, first source, second gate, and second source. Control system includes first gate drive circuit, second gate drive circuit, and controller. Controller controls first gate drive circuit and second gate drive circuit. At the time of turning on dual-gate bidirectional switch and when the potential of first source is lower than the potential of second source, controller applies a first positive voltage for a first period between first gate and first source from first gate drive circuit, and applies a voltage smaller than the first positive voltage after the first period has elapsed.

A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the barrier layer, a first layer adjacent to a first side of the p-type semiconductor layer without extending to a second side of the p-type semiconductor layer, and a second layer adjacent to the second side of the p-type semiconductor layer without extending to the first side of the p-type semiconductor layer.

The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.

Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

A power converter circuit includes a switch including a field effect transistor, the field effect transistor being a wide bandgap field effect transistor and being configured to maintain an on operational state responsive to a maintenance signal received through a gate terminal, a current sensing circuit that is configured to estimate a drain terminal current of the field effect transistor responsive to a voltage between the gate terminal of the field effect transistor and a source terminal of the field effect transistor, and a gate driving circuit that is configured to generate the maintenance signal responsive to the estimate of the drain terminal current.

A nitride semiconductor device 1 includes a first transistor 3 which is constituted of a normally-off transistor and functions as a main transistor and a second transistor 4 which is constituted of a normally-on transistor and arranged to limit a gate current of the first transistor. The first transistor 3 includes a first electron transit layer 7A constituted of a nitride semiconductor and a first electron supply layer 8A which is formed on the first electron transit layer and constituted of a nitride semiconductor. The second transistor 4 includes a second electron transit layer 7B constituted of a nitride semiconductor and a second electron supply layer 8B which is formed on the second electron transit layer and constituted of a nitride semiconductor. A gate electrode 51 and a source electrode 44 of the second transistor 4 are electrically connected to a gate electrode 16 of the first transistor 3.

Provided are a semi-conductor structure and a manufacturing method thereof. The semi-conductor structure includes: a substrate, a heterojunction, a P-type ion doped layer and a gate insulation layer disposed from bottom to top, wherein the heterojunction includes a source region, a drain region and a gate region; the P-type ion doped layer in the gate region includes an activated region and non-activated regions, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated regions are passivated; the non-activated regions include at least two regions which are spaced apart in a direction perpendicular to a connection line of the source region and the drain region; the gate insulation layer is located on the non-activated region to expose the activated region.