A semiconductor device 1 includes a trench gate structure 6 formed in a surface layer portion of a first principal surface of a semiconductor layer. A source region 10 and a well region 11 are formed in a surface layer portion of the first principal surface of the semiconductor layer at a side of the trench gate structure 6. The well region 11 is formed in a region at a side of the second principal surface of the semiconductor layer with respect to the source region 10. A channel is formed along the trench gate structure 6 in a portion of the well region 11. A multilayer region 22 is formed in a region between the trench gate structure 6 and the source region 10 in the semiconductor layer. The multilayer region 22 has a p type impurity region 20 formed in the surface layer portion of the first principal surface of the semiconductor layer and an n type impurity region 21 formed in a side of the second principal surface of the semiconductor layer with respect to the second conductivity type impurity region 20.

A semiconductor device includes a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET. The semiconductor device includes a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate. The semiconductor device includes a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate. Various example implementations of this type of semiconductor device provide a SiC power MOSFET with improved short-circuit capability and durability, with minimal impact on R.sub.DS-ON.

A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.

Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

A silicon carbide semiconductor device has an n-type silicon carbide semiconductor substrate, an n-type first semiconductor layer, n-type first JFET regions, a p-type second semiconductor layer, n-type first semiconductor regions, and trenches. The first semiconductor layer has an impurity concentration lower than that of the substrate. The first JFET regions are provided in a surface layer of the first semiconductor layer and have an effective donor concentration higher than that of the first semiconductor. The p-type second semiconductor layer is provided at a surface of the first semiconductor layer. The n-type first semiconductor regions are selectively provided in a surface layer of the second semiconductor layer. The trenches penetrate through the first semiconductor regions, the second semiconductor layer, and the first JFET regions. The first JFET regions are doped with an acceptor that is aluminum and a donor that is nitrogen or phosphorus.

A SiC semiconductor device includes a first load electrode, a normally-on junction field effect transistor, and an insulated gate field effect transistor. The normally-on junction field effect transistor includes a channel region electrically connected to the first load electrode. The insulated gate field effect transistor and the normally-on junction field effect transistor are electrically connected in series. The insulated gate field effect transistor includes a source region and a body region. The source region is electrically connected to a channel region of the normally-on junction field effect transistor. The body is electrically connected to the first load electrode.

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Aspects of the present disclosure relate to a semiconductor power device, in particular to a Silicon Carbide, SiC, Merged P-I-N Schottky (MPS) diode. The device includes an active area and a termination area adjacent the active area. The termination area includes first rings having a first polarity. By including second rings having a second polarity opposite to the first polarity, a reduced effect of interface charges on the performance of the semiconductor power device can be observed.