A set of silicon fins for n-type FinFET devices and a set of silicon germanium fins for p-type FinFET devices are provided on a strain relaxation buffer (SRB) substrate. Each fin in the set of silicon fins is cut forming a set of cut silicon fins having a set of vertical faces at a fin end of a respective cut silicon fin. Each fin in the set of silicon germanium fins is cut forming a set of cut silicon germanium fins having a set of vertical faces at a fin end of a respective silicon germanium fin. A set of tensile dielectric structures is formed. Each of the tensile dielectric structures respectively contact the vertical faces of respective fin ends of the cut silicon fins to maintain tensile strain at the fin ends of the set of cut silicon fins. A set of compressive dielectric structures are formed. Each of the compressive dielectric structures respectively contact the vertical faces of respective fin ends of the cut silicon germanium fins to maintain compressive strain at the fin ends of the set of cut silicon fins. Another aspect of the invention is a device which is created by the method.

A semiconductor device includes an N-type fin-like field effect, a P-type fin-like field effect transistor, a shallow trench isolation (STI) structure, a first interlayer dielectric (ILD) layer, and a second ILD layer. The N-type fin-like field effect transistor includes a first semiconductor fin, a gate structure across the first semiconductor fin, and a first source/drain feature in contact with the first semiconductor fin. The P-type fin-like field effect transistor includes a second semiconductor fin, the gate structure across the second semiconductor fin, and a second source/drain feature in contact with the second semiconductor fin. The structure surrounds the first and second semiconductor fins. The first interlayer dielectric (ILD) layer covers the first source/drain feature. The second ILD layer covers the second source/drain feature, wherein a porosity of the second ILD layer is greater than a porosity of the first ILD layer.

A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate structure on the fin-shaped structure and the STI and the fin-shaped structure directly under the gate structure includes a first epitaxial layer; forming a source region having first conductive type adjacent to one side of the gate structure; and forming a first drain region having a second conductive type adjacent to another side of the gate structure.

Disclosed are performance-enhanced vertical devices (e.g., vertical field effect transistors (FETs) or complementary metal oxide semiconductor (CMOS) devices, which incorporate vertical FETs) and methods of forming such devices. A strained dielectric layer is positioned laterally adjacent to the gate of a vertical FET, increasing the charge carrier mobility within the channel region and improving performance. In a vertical n-type FET (NFET), the strain is compressive to improve electron mobility given the direction of current within the vertical NFET; whereas, in a vertical p-type FET (PFET), the strain is tensile to improve hole mobility given the direction of current within the vertical PFET. Optionally, the orientation of a vertical FET relative to the surface plane of the semiconductor wafer on which it is formed is also preplanned as function of the type of FET (i.e., NFET or PFET) for optimal charge carrier mobility and, thereby enhanced performance.

The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

Controlling execution of software is provided. In response to receiving an input to execute a software module on a data processing system, a set of measurements are performed on the software module performing a process to prepare the software module for execution on the data processing system. In response to determining that the set of measurements meets a predetermined criterion, an authorization to proceed with the process of preparing the software module for execution on the data processing system is requested from a trusted third party computer. In response to receiving the authorization to proceed with the process of preparing the software module for execution on the data processing system from the trusted third party computer, the software module is executed.