Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T.sub.1 of the cap portion is greater than a thickness T.sub.2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

A method of forming a vertical transport fin field effect transistor device is provided. The method includes replacing a portion of a sacrificial exclusion layer between one or more vertical fins and a substrate with a temporary inner spacer. The method further includes removing a portion of a fin layer and the sacrificial exclusion layer between the one or more vertical fins and the substrate, and forming a bottom source/drain on the temporary inner spacer and between the one or more vertical fins and the substrate. The method further includes replacing a portion of the bottom source/drain with a temporary gap filler, and replacing the temporary gap filler and temporary inner spacer with a wrap-around source/drain contact having an L-shaped cross-section.

In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.