A semiconductor device may include first and second active regions on a substrate, first and second active patterns on the first and second active regions, first and second source/drain patterns on the first and second active patterns, first and second silicide patterns on the first and second source/drain patterns, and first and second active contacts coupled to the first and second source/drain patterns. A lowermost portion of the first active contact is at a level higher than that of a lowermost portion of the second active contact. A thickness of the first silicide pattern is greater than that of the second silicide pattern.

A semiconductor structure includes: a substrate; a conductive via, a first conductive type transistor, and a second conductive type transistor located in substrate; a first metal layer located on substrate; and a second metal layer located on first metal layer. The first conductive type transistor is disposed on two sides of conductive via in first direction, and second conductive type transistor is disposed on two other sides of conductive via in a second direction perpendicular to first direction. The first metal layer includes at least one first metal line extending in first direction and electrically connected to a gate of first conductive type transistor. The second metal layer includes at least one second metal line extending in second direction and electrically connected to a gate of second conductive type transistor. The first metal line and second metal line intersect with each other to form a grid structure covering conductive via.

Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

A semiconductor device includes a semiconductor chip which has a main surface, a first groove which is formed in the main surface and demarcates the main surface into a first region and a second region, a first insulating film which is formed on a wall surface of the first groove, a second groove which is formed in the main surface of the first region at an interval from the first groove, a second insulating film which covers an upper wall surface of the second groove and is thinner than the first insulating film, a third insulating film which covers a lower wall surface of the second groove and is thicker than the second insulating film, a third groove which is formed in the main surface of the second region at an interval from the first groove, a fourth insulating film, and a fifth insulating film.

Provided are a field effect transistor, an electronic apparatus including the same, and a method of manufacturing the field effect transistor. The field effect transistor may include a substrate; a gate electrode on the substrate; an insulating layer on the gate electrode; a source electrode on the insulating layer; a drain electrode apart from the source electrode; a channel between the source electrode and the drain electrode and including a two-dimensional (2D) material; a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode; and a stressor adjacent to the 2D material electrode bonding layer. The stressor may be configured to apply a tensile strain to the 2D material electrode bonding layer.

A method of manufacturing a semiconductor structure includes forming an active region having a first portion which is doped. The method further includes forming a first silicide layer over and electrically coupled to the first portion of the active region. The method further includes forming a second silicide layer under and electrically coupled to the first portion of the active region. The method further includes forming a first metal-to-drain/source (MD) contact structure over and electrically coupled to the first silicide layer. The method further includes forming a first via-to-MD (VD) structure over and electrically coupled to the MD contact structure. The method further includes forming a buried via-to-source/drain (BVD) structure under and electrically coupled to the second silicide layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The gate stack is partially embedded in the first nanostructure. The semiconductor device structure includes a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure includes a contact structure surrounding the first source/drain layer. A first portion of the contact structure is between the first source/drain layer and the substrate.

A method of forming a semiconductor structure includes forming at least one fin disposed over a top surface of a substrate, the fin providing a vertical transport channel for a vertical transport field-effect transistor. The method also includes forming a top source/drain region disposed over a top surface of the fin, and forming a first contact trench at a first end of the fin and a second contact trench at a second end of the fin, the first and second contact trenches being self-aligned to the top source/drain region. The method further includes forming inner spacers on sidewalls of the first contact trench and the second contact trench, and forming contact material in the first contact trench and the second contact trench between the inner spacers. The contact material comprises a stressor material that induces vertical strain in the fin.