Thin film transistors having strain-inducing structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is on the 2D material layer, the gate stack having a first side opposite a second side. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack. The first gate spacer and the second gate spacer induce a strain on the 2D material layer. A first conductive structure is on the 2D material layer and adjacent to the first gate spacer. A second conductive structure is on the 2D material layer and adjacent to the second gate spacer.

An RF MOSFET includes respective pluralities of gate fingers, source fingers, and drain fingers formed on a semiconductor structure. The gate fingers are spaced apart from each other along a first direction, extend in a second, orthogonal direction, and are electrically connected to one another through a gate mandrel. The source fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a source mandrel. The drain fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a drain mandrel. Adjacent unit cell transistors of the RF MOSFET are separated from one another by a dummy gate and a trench that extends into the semiconductor structure. The semiconductor structure may be a bulk semiconductor wafer, a PD-SOI wafer, or an FD-SOI wafer.

Techniques are described for forming strained fins for co-integrated n-MOS and p-MOS devices that include one or more defect trapping layers that prevent defects from migrating into channel regions of the various co-integrated n-MOS and p-MOS devices. A defect trapping layer can include one or more patterned dielectric layers that define aspect ratio trapping trenches. An alternative defect trapping layer can include a superlattice structure of alternating, epitaxially mismatched materials that provides an energetic barrier to the migration of defect. Regardless, the defect trapping layer can prevent dislocations, stacking faults, and other crystallographic defects present in a relaxed silicon germanium layer from migrating into strained n-MOS and p-MOS channel regions grown thereon.

In a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The transistor includes an oxide semiconductor film over a first insulating film; a second insulating film over the oxide semiconductor film; a metal oxide film over the second insulating film; a gate electrode over the metal oxide film; and a third insulating film over the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The source region and the drain region contain one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas.

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A semiconductor device includes a substrate, a first insulating layer on the substrate, source and drain patterns at spaced-apart locations on the first insulating layer, and a channel layer having a transition metal therein, such as a transition metal dichalcogenide. The channel layer extends on the first insulating layer and between the source and drain patterns. A second insulating layer is also provided, which extends on the channel layer and has a thickness less than a thickness of the first insulating layer. A gate structure is provided, which extends on the second insulating layer, and opposite the channel layer. The channel layer may include at least one of MoS.sub.2, WS.sub.2, MoSe.sub.2, WSe.sub.2, MoSe.sub.2, WTe.sub.2, and ZrSe.sub.2.

A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 10.sup.19 atoms cm.sup.−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.