Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.

A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure extends exceeding opposite sidewalls of the first epitaxial structure.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first region, and a first transistor positioned in the first region. The first transistor includes a first bottom gate structure positioned on the substrate, a first channel layer positioned on the first bottom gate structure, a first top gate structure positioned on the first channel layer, and two first source/drain regions positioned on two sides of the first channel layer.

An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

A nonplanar circuit device having a strain-producing structure disposed under the channel region is provided. In an exemplary embodiment, the integrated circuit device includes a substrate with a first fin structure and a second fin structure disposed on the substrate. An isolation feature trench is defined between the first fin structure and the second fin structure. The circuit device also includes a strain feature disposed on a horizontal surface of the substrate within the isolation feature trench. The strain feature may be configured to produce a strain on a channel region of a transistor formed on the first fin structure. The circuit device also includes a fill dielectric disposed on the strain feature within the isolation feature trench. In some such embodiments, the strain feature is further disposed on a vertical surface of the first fin structure and on a vertical surface of the second fin structure.

A finned structure is fabricated using a bulk silicon substrate having a carbon-doped epitaxial silicon germanium layer. A pFET region of the structure includes fins having silicon germanium top portions and an epitaxial carbon-doped silicon germanium diffusion barrier that suppresses dopant diffusion from the underlying n-well into the silicon germanium fin region during device fabrication. The structure further includes an nFET region including silicon fins formed from the substrate. The carbon-doped silicon germanium diffusion barrier has the same or higher germanium content than the silicon germanium fins.

Embodiments are directed to a method of forming features of a semiconductor device. The method includes forming a first feature including a first type of semiconductor material, which can be tensile or can have compressive strain. The method further includes forming an enclosure structure including a second type of semiconductor material, wherein the first feature includes first feature sidewall surfaces extending around a circumference of the first feature. The enclosure structure is adjacent at least a portion of the first feature sidewall surfaces and extends around the circumference of the first feature.

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.