A multi-gate ferroelectric memory comprises a fin-shaped channel layer, a front ferroelectric layer disposed on one side of the fin-shaped channel layer, a back ferroelectric layer disposed on another side of the fin-shaped channel layer, a front gate attached to the front ferroelectric layer and away from the fin-shaped channel layer, wherein the front gate is configured to connect a word line, and a back gate attached to the back ferroelectric layer and away from the fin-shaped channel layer, wherein the back gate is configured to connect a bit line. The present disclosure further discloses a memory array device, comprises a plurality of the multi-gate ferroelectric memories arranged as an array, a plurality of word lines and a plurality of bit lines.

Certain aspects of the present disclosure generally relate to techniques for reducing leakage current in polysilicon-on-active-edge structures. An example transistor structure includes one or more active devices and at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first metal gate stack and a second metal gate stack over the semiconductor substrate. The first metal gate stack and the second metal gate stack are electrically isolated from each other, and the first metal gate stack has a curved edge facing the second metal gate stack. The semiconductor device structure also includes a dielectric layer surrounding the first metal gate stack and the second metal gate stack.

In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.

A semiconductor device including a structure having N gate electrode layers G and (N−1) channel formation region layers CH (where N≥3) alternately juxtaposed on an insulating material layer formed on a surface of a conductive substrate. Each of the structure, the channel formation region layer CH, and the gate electrode layer G has a bottom surface, a top surface, and four side surfaces. A second surface of the n.sup.th channel formation region layer is connected to a fourth surface of the n.sup.th gate electrode layer. A fourth surface of the n.sup.th channel formation region layer is connected to a second surface of the (n+1).sup.th gate electrode layer. One of an odd-numbered layer of the gate electrode layers and an even-numbered layer of the gate electrode layers is connected to a first contact portion and the other is connected to a second contact portion.

A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.

A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.