The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

Provided are a layer structure including a configuration capable of increasing the operation characteristics of a device including the layer structure, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure includes a first layer and a second layer on one surface of the first layer and facing the first layer. The first layer and the second layer overlap each other. One layer of the first layer and the second layer has a trace of applied strain, and an other layer of the first layer and the second layer is a strain-inducing layer that applies a strain to the one layer.

Cubic BAs is used in semiconductors to improve the thermal characteristics of a device. The BAs is used in device layers to improve thermal conductivity. The BAs also provides thermal expansion characteristics that are compatible with other semiconductors and thereby further improves reliability. The substrates of the semiconductors may also include vias that contain BAs. The BAs in the vias may contact the BAs in the device layers. Some vias may have a surface area to volume ratio of greater than 10 to better assist with device heat dissipation.

Integrated circuit (IC) devices implementing pairs of thin-film transistors (TFTs) with shared contacts, and associated systems and methods, are disclosed. An example IC device may include a support structure, a channel layer provided over the support structure, where the channel layer includes a thin-film semiconductor material, a first TFT with a channel region that includes a first portion of the channel layer, and a second TFT with a channel region that includes a second portion of the channel layer. In some embodiments, a source or a drain (S/D) contact of the first TFT may be a shared contact that is also a S/D contact of the second TFT. In other embodiments, a gate contact/stack of the first TFT may be a shared contact/stack that is also a gate contact/stack of the second TFT.

Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.

Thin film transistors having semiconductor structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is above the 2D material layer, the gate stack having a first side opposite a second side. A semiconductor structure including germanium is included, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack. A first conductive structure is adjacent the first side of the second gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure. The semiconductor structure is intervening between the first conductive structure and the 2D material layer. A second conductive structure is adjacent the second side of the second gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.

A thin film transistor includes a semiconductor layer, a first gate electrode disposed at one side of the semiconductor layer, a first gate insulating layer disposed between the first gate electrode and the semiconductor layer, a second gate electrode and a third gate electrode disposed at another side of the semiconductor layer, and a second gate insulating layer. The second gate electrode is separated from the third gate electrode. The second gate insulating layer is disposed between the second and third gate electrodes and the semiconductor layer. An orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the second gate electrode on the semiconductor layer. The orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the third gate electrode on the semiconductor layer.

A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.

Provided are a thin film transistor array substrate and an electronic device including the same. More specifically, the thin film transistor array includes a first active layer including a first area, a second area spaced apart from the first area, and a channel area provided between the first area and the second area, a first gate electrode disposed on the first active layer, and a second gate electrode disposed on the same layer as the first gate electrode to overlap one end of the first gate electrode and to which a signal corresponding to a signal applied to the first gate electrode is applied. Therefore, it is possible to have a structure for simultaneously controlling the threshold voltage, mobility, and subthreshold (S) parameter of a thin film transistor.

A display device includes: a substrate configured to contain an organic material; a first underlying film provided above the substrate; a thin film transistor provided above the first underlying film; a semiconductor film included in the thin film transistor and configured to have a channel region; and an electric field inhibition film provided between the first underlying film and the semiconductor film and configured to overlap the channel region in a plan view. The electric field inhibition film has a higher permittivity than the first underlying film.