A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Provided are an image sensor and a method of manufacturing method of manufacturing the image sensor. The image sensor includes a substrate, photoelectric transducers and switching elements formed in layers on the substrate in this order. Each of the photoelectric transducers includes a hydrogenated amorphous silicon layer. Each of the switching elements includes an amorphous oxide semiconductor layer. The image sensor further includes a blocking layer arranged between the hydrogenated amorphous silicon layers of the photoelectric transducers and the amorphous oxide semiconductor layers of the switching elements, where the blocking layer suppresses penetration of hydrogen separated from the hydrogenated amorphous silicon layers.

A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film. The source and drain electrodes each includes a conductive oxide film in contact with the oxide semiconductor film. The conductive oxide film has more oxygen vacancies than the oxide semiconductor film.

The array board 11b includes a first diode 29, a common line 25, a first shorting line 31, and the static protection portion 51. The first diode 29 include at least the first semiconductor portion 29d having outer edges 29d1 that cross the outer edges 29a1, 29b1 of first electrodes 29a, 29b in a plan view. The common line 25 is formed from the first metal film 34. The first shorting line 31 is formed from the second metal film 38 and crosses the common line 25. The static protection portion 51 is formed from the second metal film 38 or the protection film 37. At least a portion of the static protection portion 51 overlaps the common line 25 in a plan view. The static protection portion 51 is arranged closer to the first diode 29 than an intersection CPT of the common line 25 and the first shorting line 31. The static protection portion 51 includes at least a static dissipating portion 52 for dissipating static.

A TFT device including: a gate electrode; a channel layer above the gate electrode; a channel protection layer on the channel layer; an electrode pair on the channel protection layer composed of a source electrode and a drain electrode that are spaced away from one another, a part of each of the source electrode and the drain electrode in contact with the channel layer through the channel protection layer; and a passivation layer extending over the gate electrode, the channel layer, the electrode pair, and the channel protection layer. The channel layer is made of an oxide semiconductor. The TFT device has a first sub-layer made of one of silicon nitride and silicon oxynitride and in which Si—H density is no greater than 2.3×10.sup.21 cm.sup.−3. The first sub-layer is included in at least one of the channel protection layer and the passivation layer.

The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

The present disclosure provides a TFT and a circuit structure to improve the characteristics of the threshold voltage drift of the TFT. The TFT includes a gate electrode, a semiconductor layer, an etch stop layer, and a source electrode and a drain electrode connected to the semiconductor layer. The TFT further includes a stopping structure arranged over the etch stop layer. The stopping structure is electrically isolated from the source electrode and the drain electrode, and an orthogonal projection of the stopping structure onto the etch stop layer at least partially overlaps an orthogonal projection of the semiconductor layer onto the etch stop layer. The present disclosure improves the characteristics of the threshold voltage drift of the TFT.

A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.

This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.