A semiconductor die includes semiconductor substrate and interconnection structure. Interconnection structure includes first conductive lines, first conductive patterns, first pillar stacks, second pillar stacks, gate patterns. First conductive lines extend parallel to each other in first direction and are embedded in interlayer dielectric layer. First conductive patterns are disposed in row along first direction and are embedded in interlayer dielectric layer beside first conductive lines. First pillar stacks include first pairs of metallic blocks separated by first dielectric material blocks. Second pillar stacks include second pairs of metallic blocks separated by second dielectric material blocks. Each second pillar stack is electrically connected to respective first conductive pattern. Gate patterns extend substantially perpendicular to first conductive lines. Each gate pattern directly contacts one respective second pillar stack and extends over a group of first pillar stacks.

A method for forming a semiconductor structure includes the following: providing a semiconductor substrate, in which stack structures and isolation structures alternately arranged along a first direction are formed on the semiconductor substrate; forming a support structure in the stack structures and the isolation structures; etching the stack structures and the isolation structures to form multiple zigzag first semiconductor pillars in an array arrangement along the first direction and a second direction, in which an interspace is formed between the zigzag first semiconductor pillars; each zigzag first semiconductor pillar comprises first convex structures and first concave structures alternately arranged along a third direction, and is supported by the support structure; the first direction, the second direction and the third direction are perpendicular to one another, and the second direction is perpendicular to a top surface of the semiconductor substrate; forming capacitor structures the interspace.

A semiconductor structure and a method for manufacturing same are provided. The semiconductor structure includes: a substrate, and a first transistor and a second transistor protruding from the substrate. The first transistor at least includes a first doped region and a second doped region arranged from bottom to top. The second transistor at least includes a third doped region and a fourth doped region arranged from bottom to top. Herein, the first doped region and the third doped region have a first conductivity type, the second doped region and the fourth doped region have a second conductivity type, and a breakdown voltage of the first transistor is smaller than a breakdown voltage of the second transistor.

Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.

A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi.sub.2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.

Memory cells with non-planar memory materials that include FE or AFE materials are described. An example memory cell includes a transistor provided over a support structure, where a memory material is integrated with a transistor gate. The channel material and the memory material are non-planar in that each includes a horizontal portion substantially parallel to the support structure, and a first and a second sidewall portions, each of which is substantially perpendicular to the support structure, where the horizontal portion of the memory material is between the horizontal portion of the channel material and a gate electrode material of the transistor gate, the first sidewall of the memory material is between the first sidewall of the channel material and the gate electrode material, and the second sidewall of the memory material is between the second sidewall of the channel material and the gate electrode material.

A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.

A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.