A display device including a plurality of thin film transistors. One of the plurality of thin film transistors includes a gate electrode, a semiconductor layer having a region overlapping the gate electrode, a gate insulating layer between the gate electrode and the semiconductor layer, a source electrode and a drain electrode in contact with a surface of the semiconductor layer opposite to the side of the gate insulating layer, and a first shield electrode arranged in a region where the source electrode and the gate electrode overlap, and a second shield electrode arranged in a region where the drain electrode and the gate electrode overlap. The first shield electrode and the second shield electrode are arranged between the gate electrode and the semiconductor layer, and are insulated from the gate electrode, the semiconductor layer, the source electrode, and the drain electrode.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.

Provided is a display device. The display device comprises a substrate, and a plurality of sub-pixels disposed on the substrate and including alight emitting element and a sub-pixel circuit driving the light emitting element. The sub-pixel circuit comprises a driving transistor controlling a driving current flowing through the light emitting element, a first transistor and a second transistor connected in series between a first node, which is a drain electrode of the driving transistor, and a second node, which is a gate electrode of the driving transistor, to receive the same scan signal, and a gate auxiliary electrode disposed on a gate electrode of the first transistor or the second transistor. The gate auxiliary electrode is connected to the gate electrode of the first transistor or the second transistor.

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

An RF MOSFET includes respective pluralities of gate fingers, source fingers, and drain fingers formed on a semiconductor structure. The gate fingers are spaced apart from each other along a first direction, extend in a second, orthogonal direction, and are electrically connected to one another through a gate mandrel. The source fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a source mandrel. The drain fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a drain mandrel. Adjacent unit cell transistors of the RF MOSFET are separated from one another by a dummy gate and a trench that extends into the semiconductor structure. The semiconductor structure may be a bulk semiconductor wafer, a PD-SOI wafer, or an FD-SOI wafer.

A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

A hybrid stacked semiconductor device includes a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion and a second stack portion. The first stack portion includes first channels. The second stack portion is stacked on the first stack portion, and includes second channels. The all-around gate includes a first gate portion that wraps around the first channels and a second gate portion that wraps around the second channels. A first gate extension contacts the first gate portion and the second gate extension contacts the second gate portion. At least one gate contact contacts the first gate extension to establish conductivity with the first gate portion and contacts the second gate extension to establish conductivity with the second gate portion.

A display device includes a substrate including a sub-pixel area, an active layer disposed in the sub-pixel area and including first to third regions, a first channel region between the first and second regions, and a second channel region between the second and third regions, a first gate electrode disposed in the first and second channel regions, and constituting a dual gate transistor together with the first and second regions, the first channel region, the second and third regions, and the second channel region, a first gate insulating layer disposed between the active layer and the first gate electrode, and defining an opening exposing the second region, an insulating pattern in the opening, a gate electrode pattern contacting a top surface of the insulating pattern, and is spaced apart from the first gate electrode, and a light emitting structure on the dual gate transistor and the gate electrode pattern.

A thin film transistor includes a semiconductor layer, a first gate electrode disposed at one side of the semiconductor layer, a first gate insulating layer disposed between the first gate electrode and the semiconductor layer, a second gate electrode and a third gate electrode disposed at another side of the semiconductor layer, and a second gate insulating layer. The second gate electrode is separated from the third gate electrode. The second gate insulating layer is disposed between the second and third gate electrodes and the semiconductor layer. An orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the second gate electrode on the semiconductor layer. The orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the third gate electrode on the semiconductor layer.

An array substrate is provided. The array substrate includes a data line; a first voltage supply line; a second voltage supply line; and a pixel driving circuit. The pixel driving circuit includes one or more transistors in a first group and one or more transistors in a second group. A source electrode and a drain electrode of at least one transistor in the first group, the data line, the first voltage supply line, and the second voltage supply line are in a same layer. A source electrode and a drain electrode of at least one transistor in the second group are in a layer different from the first voltage supply line and the second voltage supply line.