A semiconductor device with small variations in transistor characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; an insulator in a region between the first conductor and the second conductor over the oxide; and a conductor over the insulator. A side surface of the oxide, a top surface of the first conductor, a side surface of the first conductor, a top surface of the second conductor, and a side surface of the second conductor include regions in contact with a nitride containing silicon.

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

According to one embodiment, a semiconductor device includes a first insulating layer, an oxide semiconductor disposed on the first insulating layer, a second insulating layer which covers the oxide semiconductor and a gate electrode disposed on the second insulating layer and overlapping the oxide semiconductor. The oxide semiconductor includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode. The first insulating layer, the second region and the second insulating layer contain impurities of a same type. The impurities contained in a region directly below the second region in the first insulating layer are more than the impurities contained in the second region.

A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

Devices and methods for switch body connections to achieve soft breakdown. In some embodiments, a method of implementing a radio-frequency switching device can include providing an assembly of source, gate, and drain implemented on an active region; providing a first body contact implemented at a first end of the assembly; and providing a second body contact implemented at a second end of the assembly, the second end distal from the first end along a width of the radio-frequency switching device.

A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

A method for forming a semiconductor device structure is provided. The method includes forming first nanostructures and second nanostructures over a semiconductor substrate. The method also includes forming a dielectric fin between the first nanostructures and the second nanostructures. The method further includes forming a metal gate stack wrapped around the first nanostructures, the second nanostructures, and the dielectric fin. In addition, the method includes forming an insulating structure penetrating into the metal gate stack and aligned with the dielectric fin.

Provided is a display substrate, including: a silicon-based substrate having a display area, a binding area located on one side of the display area, and a trace area located between the display area and the binding area; a trace protection structure is arranged on the silicon-based substrate in the trace area, and a pad assembly is integrated in the silicon-based substrate in the binding area; and a minimum distance between an edge of an orthographic projection of the trace protection structure on the silicon-based substrate and an edge of an orthographic projection of an opening of the pad assembly on the silicon-based substrate is smaller than a maximum size of one subpixel.

Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures are described. An integrated circuit structure includes a first gate stack over a first fin, and a second gate stack over a second fin. First and second epitaxial source or drain structures are at first and second ends of the first fin. Third and fourth epitaxial source or drain structures are at first and second ends of the second fin. A first conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures, and has a first portion partitioned from a second portion. A second conductive contact structure is coupled to one of the third or the fourth epitaxial source or drain structures, and has a first portion partitioned from a second portion. The second conductive contact structure is neighboring the first conductive contact structure and has a composition different than a composition of the first conductive contact structure.

A semiconductor device structure is provided, which includes a first fin structure over a semiconductor substrate. The first fin structure has multiple first semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a second fin structure over the semiconductor substrate, and the second fin structure has multiple second semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a dielectric fin between the first fin structure and the second fin structure. In addition, the semiconductor device structure includes a metal gate stack wrapping around the first fin structure, the second fin structure, and the dielectric fin. The semiconductor device structure includes a dielectric protection structure over the metal gate stack. The semiconductor device structure also includes an insulating structure penetrating through a bottom surface of the dielectric protection structure and extending into the metal gate stack to be aligned with the dielectric fin.