The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a first transition metal dichalcogenide film on a substrate; a second transition metal dichalcogenide film on the first transition metal dichalcogenide film; source and drain features formed over the second transition metal dichalcogenide film; and a first gate stack formed over the second transition metal dichalcogenide film and interposed between the source and drain feature.

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

A process for fabricating a vertical transistor is provided, including steps of providing a substrate surmounted by a stack of first to third layers made of first to third semiconductors materials of two different types; partially etching the first and third layers with an etching that is selective, so as to form a first void in the first layer and a third void in the third layer, extending to the lower surface and to the upper surface of the second layer, respectively; filling the voids in order to form spacers making contact with the lower surface and the upper surface, respectively; partially etching the second layer with an etching that is selective, so as to form a second void between the first and second spacers; and depositing a conductor material in the second void.

Semiconductor structures and methods for forming the same are provided. The method includes forming a well region in a substrate and forming an anti-punch through region in a top portion of the well region. The method further includes forming a barrier layer over the anti-punch through region and alternately stacking first semiconductor material layers and second semiconductor material layers over the barrier layer. The method further includes patterning the first semiconductor material layers, the second semiconductor material layers, the barrier layer, and the anti-punch through region to form a fin and removing the first semiconductor material layers and the barrier layer to expose the anti-punch through region. The method further includes forming a gate wrapping around the second semiconductor material layers.

Embodiments herein describe FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (a male portion of the female/male connection) in order to connect the channels to the drain and source regions. In one embodiment, a first conductive contact is formed underneath a dummy channel. In addition an encapsulation material wraps around the first conductive contact. The dummy channel and the encapsulation material can then be removed and replaced by the material of the channel which, as a result, include a female portion that wraps around the first conductive contact.

Embodiments herein describe FETs with channels connected on the sides to a metal liner. To avoid the difficulties of connecting the sides of the channels to metal liners for the drain and source regions, the embodiments herein form a male/female contact between the channels and the metal liners. In one embodiment, instead of exposing only the end or side surfaces of the channels, an end knob of the channel is exposed. This knob can include the side surface as well as a portion of the top, bottom, front, and back sides of the channel. As such, when the metal liner is deposited on the knob, this metal forms an electrical connection on all sides of the knob. This male/female connection provides a more reliable and lower resistance connection between the channel and the metal liner than using only the end or side surfaces of the channel.

Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

An apparatus and method wherein the apparatus comprises: a sensing material configured to produce a non-random distribution of free charges in response to a parameter; an electric field sensor; a first conductive electrode comprising a first area over-lapping the sensing material; an insulator provided between the first conductive electrode and the sensing material; a second electrode comprising a second area adjacent the electric field sensor; and a conductive interconnection between the first conductive electrode and the second conductive electrode.