An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

A memory cell includes a substrate and a body including plural layers. The body has an inner body and an outer body, and the body is formed on top of the substrate. A nanotube trench is formed vertically in the body and extends to the substrate. A nanotube structure is formed in the nanotube trench. The nanotube trench divides the body into the inner body and the outer body and the nanotube structure is mechanically separated from the inner body and the outer body by a tunnel oxide layer, a charge trapping layer, and a blocking oxide layer.

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

Aspects of the disclosure provide a memory system, a semiconductor device and fabrication method for the semiconductor device. The semiconductor device includes a memory stack with gate layers and insulating layers, and the gate layers and the insulating layers are stacked alternatingly. The semiconductor device also includes a first channel structure formed in a first channel hole in the memory stack. The first channel structure includes a channel plug in connection with a channel layer of the first channel structure. The semiconductor device also includes an isolation stack including a landing liner layer and an isolation layer. A first portion of the landing liner layer is laid on the channel plug. The semiconductor device includes a first contact structure formed in the isolation stack. The first contact structure is connected to the channel plug via an opening in the first portion of the landing liner layer.

Example implementations can include a device with a core including a first dielectric material, the core having a mesa structure, a first layer disposed over opposite faces of the mesa structure of the core, the first layer including a metal material, and a second layer disposed over the mesa structure of the core and the first layer, the second layer including a two-dimensional material. Example implementations can include a method of manufacturing a stackable semiconductor device with a two-dimensional material layer, by depositing, over a substrate, a base layer including a first dielectric material, forming, on the base layer, at least one core having a mesa structure, forming sidewalls on opposite vertical surfaces of the mesa structure of the core, depositing, over the core and the sidewalls, a semiconductor layer including a two-dimensional material, and encapsulating the core, the sidewalls, and the semiconductor layer.

A semiconductor device may include a first dielectric layer, a first gate electrode, a first gate dielectric layer, a first source electrode, a first drain electrode, and a first two-dimensional (2D) semiconductor layer. The first dielectric layer may have a first top surface. The first gate electrode may extend from the first top surface into the first dielectric layer. The first gate dielectric layer may be disposed on the first gate electrode and have a second top surface. The first source electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first drain electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first 2D semiconductor layer may be disposed on the first gate dielectric layer.

A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO.sub.2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.

A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes gate electrode layers and interlayer insulation structures that are alternately stacked with each other. The semiconductor device includes a dielectric structure disposed over the substrate to contact a sidewall surface of the gate structure, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. Each of the interlayer insulation structure includes an insulation layer and a metal-organic framework layer that are disposed on the same plane.

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a first channel structure and a second channel structure, extending in a first direction; a third channel structure disposed between the first channel structure and the second channel structure, the third channel structure extending in the first direction; and a plurality of conductive layers surrounding the first channel structure, the second channel structure, and the third channel structure, the plurality of conductive layers being stacked to be spaced apart from each other in the first direction. The third channel structure is spaced apart from the first channel structure and the second channel structure without interposition of the plurality of conductive layers.

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.