A Vertical Function Field Effect Transistor (VIFET) is disclosed with reduced noise and input capacitance and high input impedance. The VIFET has a substrate; a source disposed on the substrate; a drain, and a channel. The vertical channel has one or more channel sidewall surfaces. The channel sidewall surfaces have a total or aggregate channel sidewall surface area. A semiconductor gate grown on one or more of the channel sidewall surfaces has a thickness below 10 nanometers (nm), or between 3 am and 10 om, that reduces transistor noise. The interface surface area between the conductive (e.g. metal) external electrical gate contact and the contacted surface of the semiconductor gate is minimized to further reduce transistor noise.

An object is to provide a technology for enabling prevention of deterioration of characteristics of an oxide semiconductor device. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, a p-type oxide semiconductor layer, and an oxide layer. The p-type oxide semiconductor layer is disposed above the n-type gallium oxide epitaxial layer, contains an element different from gallium as a main component, and has p-type conductivity. The oxide layer is disposed between the n-type gallium oxide epitaxial layer and the p-type oxide semiconductor layer, and is made of a material different from gallium oxide and different at least partly from a material of the p-type oxide semiconductor layer.

A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.

An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

A method for manufacturing a semiconductor device having a junction field effect transistor, includes: preparing a substrate having a first conductivity type drift layer; forming a first conductivity type channel layer above the drift layer by an epitaxial growth, to thereby produce a semiconductor substrate; forming a second conductivity type gate layer within the channel layer by performing an ion-implantation; forming a second conductivity type body layer at a position separated from the gate layer within the channel layer by performing an ion-implantation; and forming a second conductivity type shield layer at a position that is to be located between the gate layer and the drift layer within the channel layer by performing an ion-implantation. The shield layer is formed to face the gate layer while being separated from the gate layer, and is kept to a potential different from that of the gate layer.

A semiconductor film containing silicon that is evenly doped in the semiconductor film with an enhanced semiconductor property and a method of the semiconductor film using a dopant material containing a complex compound that contains at least silicon and a halogen. The complex compound further contains a hydrocarbon group that is optionally substituted or heterocyclic group that is optionally substituted. A semiconductor film containing Si doped into the semiconductor film as a dopant to a depth that is at least 0.3 μm or deeper from a surface of the semiconductor film is obtained by forming the semiconductor film in that the dopant material is doped, the semiconductor film is 100 μm or less in film thickness with carrier density that is 1×10.sup.20/cm.sup.3 or less and electron mobility that is 1 cm.sup.2/Vs or more.

A crystalline oxide semiconductor with excellent crystalline qualities that is useful for semiconductors requiring heat dissipation is provided. A crystalline oxide semiconductor including a first crystal axis, a second crystal axis, a first side, and a second side that is shorter than the first side, a linear thermal expansion coefficient of the first crystal axis is smaller than a linear thermal expansion coefficient of the second crystal axis, a direction of the first side is parallel and/or substantially parallel to a direction of the first crystal axis, and a direction of the second side is parallel and/or substantially parallel to a direction of the second crystal axis.

A Vertical Junction Field Effect Transistor (VJFET) is disclosed with reduced noise and input capacitance and high input impedance. The VJFET has a substrate; a source disposed on the substrate; a drain; and a channel. The vertical channel has one or more channel sidewall surfaces. The channel sidewall surfaces have a total or aggregate channel sidewall surface area. A semiconductor gate grown on one or more of the channel sidewall surfaces has a thickness below 10 nanometers (nm), or between 3 nm and 10 nm, that reduces transistor noise. The interface surface area between the conductive (e.g. metal) external electrical gate contact and the contacted surface of the semiconductor gate is minimized to further reduce transistor noise.

A semiconductor device includes a drift layer, a channel layer, a source layer being the first conductivity type, a gate layer, a body layer, a shield layer and a drain layer. The channel is disposed on the drift layer. The source layer is disposed on a surface layer portion of the channel layer. The gate layer is arranged to be deeper than the source layer. The body layer is arranged to be deeper than the source layer. The shield layer is disposed at a portion of the channel layer between the gate layer and the drift layer. The shield layer is maintained at a potential different from a potential of the gate layer. The drain layer is disposed at a side opposite to the channel layer. A depth ratio of a depth of the gate layer to a depth of the body layer is equal to or larger than 0.45.