A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.

Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.

A multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device. The multilayer structure comprises: a substrate having an electrically conductive portion thereon; a dielectric layer formed over the substrate; the dielectric layer comprising an opening over at least part of the electrically conductive portion; and a conductive pillar formed on the at least part of the electrically conductive portion; wherein the conductive pillar comprises walls defined by at least the opening of the dielectric layer and an opening of a patterned layer.

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.

A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

A semiconductor device includes a substrate including, on a surface thereof, a first conductive pad and a first insulating layer formed around the first conductive pad, a semiconductor chip including, on a surface thereof, a second conductive pad and a second insulating layer around the second conductive pad, an intermediate layer formed between the substrate and the semiconductor chip, and including a conductive portion between the first and second conductive pads, and an insulating portion between the first and second insulating layers, and a molecular bonding layer formed between the substrate and the intermediate layer, and including at least one of a first molecular portion covalently bonded to a material of the first conductive pad and a material of the conductive portion, and a second molecular portion covalently bonded to a material of the first insulating layer and a material of the insulating portion.