In an embodiment a method includes providing the first component part with a partially exposed first insulating layer, a plurality of first through-vias and an exposed first contact layer structured in places and planarized in places, wherein the first through-vias are each laterally enclosed by the first insulating layer, and wherein the first contact layer partially covers the first insulating layer and completely covers the first through-vias; providing the second component part with a partially exposed second insulating layer, a plurality of second through-vias and an exposed second contact layer structured in places and planarized in places, wherein the second through-vias are each laterally enclosed by the second insulating layer, and wherein the second contact layer partially covers the second insulating layer and completely covers the second through-vias and joining the component parts such that the contact layers overlap each other thereby mechanically and electrically connecting the component parts to each other by a direct bonding process at the contact layers.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

The present invention provides a display device comprising: a substrate; a wiring electrode disposed on the substrate; a plurality of semiconductor light emitting elements each provided with a conductive electrode electrically connected to the wiring electrode; and an anisotropic conductive layer which is disposed between the conductive electrodes and the wiring electrode and formed of a mixture of conductive particles and an insulating material, wherein the conductive electrodes are provided with a protrusion part protruding toward the wiring electrode.

A high-resolution display device is provided. A display device having both high display quality and high resolution is provided. The display device is provided with a structure that inhibits a reduction in contrast due to the light guided by a layer extending across light-emitting elements. A structure body that absorbs or reflects visible light is provided between adjacent light-emitting elements. This structure body absorbs or reflects the light emitted from a light-emitting element and traveling toward an adjacent pixel, whereby a reduction in contrast due to stray light is inhibited.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A display device includes an array substrate, a plurality of mounting electrodes provided to the array substrate, a columnar conductor for coupling provided to each of the mounting electrodes, a plurality of light-emitting elements provided to the array substrate, a first electrode and a second electrode provided to a surface of each of the light-emitting elements facing the array substrate, the first electrode being coupled to one of an anode and a cathode of the light-emitting element, the second electrode being coupled to the other of the anode and the cathode of the light-emitting element, and a coupling member covering each of the first electrode and the second electrode. The columnar conductor is made of material harder than the coupling member, and an end of the columnar conductor on the light-emitting element side is electrically coupled to the coupling member.

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

In an embodiment a composite semiconductor component includes a carrier substrate having a plurality of projecting elements projecting from a first main surface of the carrier substrate, an electrically conductive material electrically conductively connected to a contact region of the carrier substrate and located on at least one of the projecting elements, some of the projecting elements not being covered with the electrically conductive material and a semiconductor chip arranged on the carrier substrate and having at a first surface at least one contact pad electrically connected to the electrically conductive material on at least one element, wherein, at a position at which the contact pad and the electrically conductive material on the projecting element are in each case in contact with one another, the contact pad has a larger lateral extent than the projecting element in each case.

A sensor array and a read-out circuit are prepared. The sensor array and the read-out circuit are aligned such that each first electrode and each second electrode face each other in a state where a connection material is disposed between a second area of the sensor array and a fourth area of the read-out circuit. The read-out circuit is pressed against the sensor array with a first load such that the sensor array and the readout circuit are bonded by the connection material with a gap provided between each first electrode and each second electrode. The read-out circuit is pressed against the sensor array with a second load larger than the first load so that each first electrode and each second electrode are connected. Before the pressing with the second load, either one of the first electrode and the second electrode has a conical shape.

Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.