Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

A light emitting device including a first LED stack, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, and a common electrode electrically connected to a first conductivity type semiconductor layer of each of the first, second, and third LED stacks, in which the common electrode includes a step in at least one of the first, second and third LED stacks.

A semiconductor device includes a carrier and a metallic structure including a metallic member, a pad and a via portion; wherein the metallic member is disposed inside the carrier, the pad is configured for receiving a solder bump and is disposed on a surface of the carrier, the via portion is configured for electrically connecting the metallic member and the pad, and the via portion is disposed proximal to an end of the pad. Further, a method of manufacturing a semiconductor device includes providing a carrier, removing a portion of the carrier for forming a via extending a surface of the carrier to an interior of the carrier, filling the via by a conductive material, and disposing the conductive material on the surface of the carrier, wherein the via is disposed proximal to an end portion of the conductive material.

Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.

A half-bridge circuit package structure includes a chip pad, a first metal island, a driving chip, an upper bridge switch, and a lower bridge switch. The driving chip includes a ground pad and a high side ground pad. The upper bridge switch includes a first enhancement mode transistor and a first depletion mode transistor. A drain pad of the first depletion mode transistor is electrically connected to the first metal island. The lower bridge switch includes a second enhancement mode transistor and a second depletion mode transistor. A source pad of the second depletion mode transistor is electrically connected to a drain pad of the second enhancement mode transistor. A drain pad of the second depletion mode transistor is electrically connected to the first metal island.

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

A display device includes a first substrate including a display area, a non-display area, and a plurality of pixel circuit units in the display area and the non-display area, a plurality of light emitting elements on the first substrate in the display area, the plurality of light emitting elements being electrically connected to the pixel circuit units, a hole mask layer on the first substrate and including a plurality of holes corresponding to the light emitting elements, a second substrate on the hole mask layer and including a plurality of open holes corresponding to the plurality of holes, and a plurality of light exit patterns in the plurality of the open holes of the second substrate corresponding to the plurality of holes, wherein each of the light exit patterns includes a first part in one of the plurality of open holes.