A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.

An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.

A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.

A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.

A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

A manufacturing method of a sensor chip package structure is provided. In the manufacturing method, a wafer including a plurality of sensor chips is provided, and each sensor chip has an active region and defines a pre-thinned region thereon. Each pre-thinned region is located at one side of the active region and covers a boundary line of each sensor chip. The pre-thinned region of each sensor chip is etched to form a concave portion. A redistribution layer is formed on the wafer. Subsequently, the wafer is cut to separate the sensor chips from one another, and each separated sensor chip has a wiring layer extending from the active region along a sidewall surface to a bottom surface of the concave portion. The separated sensor chips are respectively mounted on a plurality of substrates, and the active region is electrically connected to the substrate through the wiring layer.

The present disclosure provides a microcontroller unit and its fabrication method. The microcontroller unit includes a logic control substrate, and also includes at least one memory die and at least one non-memory die, which are disposed on the logic control substrate. The logic control substrate includes a semiconductor device layer and an interconnection dielectric layer. A central processing unit and at least one logic controller are formed in the semiconductor device layer. All memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another, and the at least one memory die is electrically connected to the central processing unit through a corresponding electrical interconnection structure in the interconnection dielectric layer. All non-memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another and are electrically connected to corresponding logic controllers through corresponding electrical interconnection structures in the interconnection dielectric layer.

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.