A semiconductor device package includes a first substrate having a first surface, a first electrical contact disposed on the first surface of the first substrate, a second substrate having a second surface facing the first surface of the first substrate, and a second electrical contact disposed on the second surface of the second substrate. The first electrical contact has a base portion and a protrusion portion. The second electrical contact covers at least a portion of the protrusion portion of the first electrical contact. The second electrical contact has a first surface facing the first substrate and a second surface facing the second substrate. A slope of a first interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the first surface of the second electrical contact is substantially the same as a slope of a second interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the second surface of the second electrical contact. A method of manufacturing a semiconductor device package is also disclosed.

A wiring structure includes a redistribution layer and an electrical pad. The redistribution layer includes a passivation layer and a metal layer. The metal layer is embedded in the passivation layer, and the passivation layer defines an opening to expose a portion of the metal layer. The electrical pad is disposed in the opening of the passivation layer and on the metal layer. The electrical pad includes a seed layer, a conductive layer, a barrier layer and an anti-oxidation layer.

This application is directed to a semiconductor system including a substrate, an electronic device, a plurality of compliant interconnects and a support structure. The substrate has a first surface and a plurality of first contacts formed on the first surface. The electronic device has a second surface facing the first surface of the substrate, and a plurality of second contacts formed on the second surface. The compliant interconnects are disposed between the first surface of the substrate and the second surface of the electronic device, and are configured to electrically couple the first contacts on the first surface of the substrate to the second contacts on the second surface of the electronic device. The support structure is coupled to the substrate and the electronic device, and extends beyond a footprint of the electronic device. The support structure is configured to mechanically couple the electronic device to the substrate.

A semiconductor package includes a semiconductor chip including a body, a connection pad, a passivation film, a first connection bump disposed, and a first coating layer; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer, a redistribution layer, and a connection via. The first connection bump includes a low melting point metal, the redistribution layer and the connection via include a conductive material, and the low melting point metal has a melting point lower than a melting point of the conductive material.

A wiring structure includes a redistribution layer and an electrical pad. The redistribution layer includes a passivation layer and a metal layer. The metal layer is embedded in the passivation layer, and the passivation layer defines an opening to expose a portion of the metal layer. The electrical pad is disposed in the opening of the passivation layer and on the metal layer. The electrical pad includes a seed layer, a conductive layer, a barrier layer and an anti-oxidation layer.

Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder.

A wiring structure includes a redistribution layer and an electrical pad. The redistribution layer includes a passivation layer and a metal layer. The metal layer is embedded in the passivation layer, and the passivation layer defines an opening to expose a portion of the metal layer. The electrical pad is disposed in the opening of the passivation layer and on the metal layer. The electrical pad includes a seed layer, a conductive layer, a barrier layer and an anti-oxidation layer.

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.