In a method for manufacturing a radiation detector, counter pixel electrodes 33 are formed on a counter substrate 2 at positions facing a plurality of pixel electrodes formed on a signal reading substrate, and wall bump electrodes 34 are further formed on the counter pixel electrodes 33. In order to achieve the above, a resist R is applied, and the resist R is exposed to light to form openings O. When Au sputter deposition is performed on the openings O, only some of the Au is deposited on the bottom surface in the openings O as the counter pixel electrodes 33. The rest of the Au is not deposited on the bottom surface in the openings O, and the most of the remaining Au adheres to the inner walls of the openings O to form wall bump electrodes 34. The bump electrodes 34 are cylindrical, making it possible to reduce the pressure acting on the signal reading substrate by an extent corresponding to the decrease in the bonding area in comparison to conventional bump-shaped bump electrodes. The decrease in the bonding area also makes it possible to correspondingly improve the reproducibility of forming the diameter of the electrodes, and make reliable connection possible.

The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.

A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

Embodiments disclosed herein include an interconnect. In an embodiment, the interconnect comprises a substrate and a pad over the substrate. In an embodiment, a hole is provided through the pad. In an embodiment, the hole exposes a portion of the substrate. In an embodiment, a solder is provided over the pad, and the solder bridges across the hole through the pad.

Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

Provided is a method of manufacturing a semiconductor device including a bump interconnect structure. In the method of manufacturing the semiconductor device, a first substrate including a connection pad is formed, and a bump including a solder layer and a metal post protruding from the solder layer are formed on the connection pad. A second substrate including a bump land may be formed. The first substrate may be disposed on the second substrate so that a protruding end of the metal post contacts the bump land, and the solder layer may be reflowed. Accordingly, it possible to interconnect the metal post to the bump land.

Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

A substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed adjacent to the first surface of the dielectric layer. The second circuit layer is disposed adjacent to the second surface of the dielectric layer and electrically connected to the first circuit layer. The second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads. The at least one conductive pillar is tapered toward the second circuit layer and disposed on one of the pads. A portion of the second surface of the dielectric layer is exposed from the second surface layer.