A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

A semiconductor package includes a semiconductor chip including a body, a connection pad, a passivation film, a first connection bump disposed, and a first coating layer; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer, a redistribution layer, and a connection via. The first connection bump includes a low melting point metal, the redistribution layer and the connection via include a conductive material, and the low melting point metal has a melting point lower than a melting point of the conductive material.

A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder.

A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.

Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having a plated film formed in the inner surface. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are selectively present at a position where the through holes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through holes are connected by the conductive particles, and the semiconductor substrates each having the through hole are bonded by an insulating adhesive.

A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.

A semiconductor package including a first die, through electrodes penetrating the first die, a first pad on a top surface of the first die and coupled to a through electrode, a second die on the first die, a second pad on a bottom surface of the second die, a first connection terminal connecting the first pad to the second pad, and an insulating layer that fills a region between the first die and the second die and encloses the first connection terminal. The first connection terminal includes an intermetallic compound made of solder material and metallic material of the first and second pads. A concentration of the metallic material in the first connection terminal is substantially constant regardless of a distance from the first pad or the second pad.

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.