A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

A memory device, a semiconductor device and their manufacturing methods are provided. One of the methods may include: providing a first die and a plurality of second dies, the first die having a first pad, each of the plurality of second dies having a second pad; stacking the plurality of second dies on the first die, the second pads and the first pad arranged in a stepwise manner, and projections of the second pads of any two adjacent second dies on the first die partially overlapped; forming a connecting hole passing through the second dies; and forming a conductive body filling the connecting hole and connecting the first pad and the second pads. This method simplifies the manufacturing process of a semiconductor device, reduces the cost thereof, and improves the production yield.

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.

Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.

A semiconductor package includes a support member including a resin body having a first surface and a second surface opposing each other and having a cavity, and at least one passive component embedded in the resin body and having a connection terminal exposed from the first surface; a first connection member disposed on the first surface of the resin body, and having a first redistribution layer on the first insulating layer and connected to the connection terminal; a second connection member disposed on the first connection member and covering the cavity, and having a second redistribution layer on the second insulating layer and connected to the first redistribution layer; and a semiconductor chip disposed on the second connection member in the cavity.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.

An electronics package includes an insulating substrate, a first electrical component coupled to a bottom surface of the insulating substrate, and a first conductor layer formed adjacent the bottom surface of the insulating substrate. The electronics package also includes a second conductor layer formed on a top surface of the insulating substrate and extending through a plurality of vias in the insulating substrate to electrically couple with the first electrical component and the first conductor layer. A second electrical component is electrically coupled to the first conductor layer and the first electrical component and the second electrical component are positioned in a stacked arrangement.

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.