In a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, CTE mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. The air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.

A method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. The transistor is farther away from the semiconductor substrate than the metal layer. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.

Some embodiments relate to an integrated circuit (IC) device including a substrate, a plurality of electrically conductive structures disposed over the substrate and separated from each other, and at least one electrically insulating structure disposed over the substrate and directly contacting each of the plurality of electrically conductive structures. The at least one electrically insulating structure has a thermal conductivity greater than five watts per meter-Kelvin (W/m-K).