An electronic component includes a circuit substrate, a connecting electrode, a micro-element, and a solder. The connecting electrode is located on the circuit substrate. The connecting electrode has a first transparent conductive layer. A surface of the first transparent conductive layer is located opposite the circuit substrate, and has a plurality of micrometers or nanometer particles. The micro-element is electrically connected to the connecting electrode. The solder is located between the connecting electrode and the micro-element, and fixes the micro-element on the connecting electrode.

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

In a semiconductor device, a first semiconductor chip and a second semiconductor chip are disposed between a first support member and a second support member. A first underlayer bonding material is disposed between the first semiconductor chip and the first support member. A second underlayer bonding material is disposed between the second semiconductor chip and the first support member. A first upper layer bonding material is disposed between the first semiconductor chip and the second support member. A second upper layer bonding material is disposed between the second semiconductor chip and the second support member.

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

Processes for adjusting dimensions of dielectric bond line materials in stacks of microelectronic components, and related material films, articles and assemblies.

A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

A method for manufacturing a micro light emitting diode (LED) display is provided. The method includes a first operation of applying a light-to-heat conversion layer to a first surface of a carrier substrate, a second operation of forming a first adhesive layer on the light-to-heat conversion layer a third operation of aligning a plurality of micro LED chips on the first adhesive layer, a fourth operation of positioning the plurality of micro LED chips above a circuit board at a first distance, a fifth operation of radiating a laser to the plurality of micro LED chips, and a sixth operation of causing the first adhesive layer to be deformed by the light-to-heat conversion layer, so that the plurality of micro LED chips are detached from the first adhesive layer to be attached to the circuit board. Various other embodiments are possible.