The disclosure relates to the field of display technologies and particularly to a chip, a flexible display panel and a display device. The chip includes a body and a plurality of connection terminals arranged on a surface of the body, where each connection terminal is provided with a stress concentration resisting structure for preventing from producing the stress concentration phenomenon.

A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group.

The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.

Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Provided are anisotropic conductive materials, electronic devices including anisotropic conductive materials, and/or methods of manufacturing the electronic devices. An anisotropic conductive material may include a plurality of particles in a matrix material layer. At least some of the particles may include a core portion and a shell portion covering the core portion. The core portion may include a conductive material that is in a liquid state at a temperature greater than 15 C. and less than or equal to about 110 C. or less. For example, the core portion may include at least one of a liquid metal, a low melting point solder, and a nanofiller. The shell portion may include an insulating material. A bonding portion formed by using the anisotropic conductive material may include the core portion outflowed from the particle and may further include an intermetallic compound.

A bonding structure comprising a contact pad, an anisotropic conductive film (ACF) and a contact structure is provided. The contact pad includes at least one recess, wherein a thickness of the contact pad is T, and a width of the at least one recess is B, The ACF is disposed on the contact pad and includes a plurality of conductive particles; each of the conductive particles is disposed in the at least one recess. A diameter of the conductive particles is A, and A is larger than B and T and satisfies B2(ATT.sup.2).sup.1/2. The contact structure is disposed on the ACF and electrically connected to the contact pad via the conductive particles. The disclosure also provides a flexible device including a substrate, a patterned insulating layer, at least one contact pad, ACF, and a contact structure.

Provided are anisotropic conductive materials, electronic devices including anisotropic conductive materials, and/or methods of manufacturing the electronic devices. An anisotropic conductive material may include a plurality of particles in a matrix material layer. At least some of the particles may include a core portion and a shell portion covering the core portion. The core portion may include a conductive material that is in a liquid state at a temperature greater than 15 C. and less than or equal to about 110 C. or less. For example, the core portion may include at least one of a liquid metal, a low melting point solder, and a nanofiller. The shell portion may include an insulating material. A bonding portion formed by using the anisotropic conductive material may include the core portion outflowed from the particle and may further include an intermetallic compound.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

A semiconductor package includes a base chip, at least one semiconductor chip disposed on the base chip, bump structures disposed between the base chip and the at least one semiconductor chip, an underfill layer surrounding the bump structures, the underfill layer having first pits in a surface thereof, and a first encapsulant in contact with a side surface of the at least one semiconductor chip and the surface of the underfill layer, on the base chip. At least some first pits, among the first pits, are connected to each other to form a first pit tunnel leading inwardly from the surface. At least a portion of the first encapsulant fills the first pit tunnel.