The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A semiconductor package includes a first substrate including silicon, a first insulating layer in contact with the first substrate, the first insulating layer including silicon oxide, the first insulating layer having a first concentration of silicon, a second insulating layer in contact with the first insulating layer, the second insulating layer including silicon oxide, the second insulating layer having a second concentration of silicon, the second concentration lower than the first concentration, and a structure on the second insulating layer. The first concentration is a ratio of a weight of silicon in the first insulating layer to a total weight of the first insulating layer, the second concentration is a ratio of a weight of silicon in the second insulating layer to a total weight of the second insulating layer, and the first concentration is in a range from 20 wt % to 50 wt %.

Embodiments of the present disclosure include a thinned device structure and method of forming a thinned device structure. Embodiments of the disclosure provided herein include the use of engineered epitaxial (Epi) layers that are formed on a base substrate. The engineered epitaxial layers include two or more epitaxial layers that each include materials that allow at least one of the two or more epitaxial layers to be selectively removed from the other layer(s). In some embodiments, one of the two or more formed epitaxial layers has etch selectivity (e.g., wet and/or dry etch selectivity) to materials disposed on either side of the formed layer.

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding.

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding.