An electronic device includes: a first semiconductor die having a metal region; a substrate having a plurality of metal regions; a first soldered joint between the metal region of the first semiconductor die and a first metal region of the substrate, the first soldered joint having one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the first semiconductor die and the first metal region of the substrate; and a second semiconductor die soldered to the first or different metal region of the substrate.

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

A transistor device structure may include a submount, a transistor device on the carrier submount, and a metal bonding layer between the submount and the transistor die, the metal bonding stack providing mechanical attachment of the transistor die to the submount. The metal bonding stack may include gold, tin and nickel. A weight percentage of a combination of nickel and tin in the metal bonding layer is greater than 50 percent and a weight percentage of gold in the metal bonding layer is less than 25 percent.

A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

Provides is a laser bonding method. The method includes forming a bonding part on a substrate; aligning a bonding target on the bonding part and bonding the bonding part and the bonding target. The bonding includes heating the bonding part using a laser. The bonding part formed on the substrate includes an adhesive layer and a conductive particle located in the adhesive layer.

The present disclosure relates to a microelectronics package with significantly reduced delamination/cracking at solder joints, and a process for making the same. The disclosed microelectronics package includes a carrier, a solder joint region over the carrier, a top intermetallic (IMC) layer over the solder joint region, and a device die over the top IMC layer. Herein, the device die includes a substrate, an active device over the substrate, a top barrier layer underneath the substrate, and a backside metal layer vertically between the top IMC layer and the top barrier layer. The backside metal layer is formed of gold (Au) with a thickness at least 0.5 μm. The top IMC layer comprises gold nickel tin (AuNiSn) or gold platinum tin (AuPtSn), and the solder joint region comprises an Au-rich gold-tin (Au.sub.5Sn) and gold-tin (AuSn) eutectic mixture.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A semiconductor device includes a semiconductor die with a metallization layer including a first metal with a comparatively high melting point, a die carrier including a second metal with a comparatively high melting point, a first intermetallic compound arranged between the semiconductor die and the die carrier and including the first metal and a third metal with a comparatively low melting point, a second intermetallic compound arranged between the first intermetallic compound and the die carrier and including the second metal and the third metal, and precipitates of a third intermetallic compound arranged between the first intermetallic compound and the second intermetallic compound and including the third metal and a fourth metal with a comparatively high melting point.