Patent classifications
H01L2224/3315
OPEN CAVITY BRIDGE CO-PLANAR PLACEMENT ARCHITECTURES AND PROCESSES
Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.
Optical semiconductor element
Provided is an optical semiconductor element in which an unbonded portion between an optical semiconductor chip and a submount is made small, heat dissipation efficiency becomes high, and service life can be made long. The optical semiconductor element can include: a submount; a submount electrode provided on a mounting surface of the submount and having a rectangular shape as a whole; and a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the submount electrode via a bonding layer. The chip electrode has a shape with chipped corners corresponding to four corners of the submount electrode, which has an exposed surface that is a portion exposed from the chip electrode at the four corners and bonded to the chip electrode to coincide with each other. The bonding layer extends to all the four corners of the exposed surface.
Semiconductor device and method for manufacturing the same
A semiconductor substrate (1) has a front surface and a rear surface facing each other. A gate wiring (2) and first and second front surface electrodes (3,4) are provided on the front surface of the semiconductor substrate (1). The first and second front surface electrodes (3,4) are separated from each other by the gate wiring (2). An insulating film (7) covers the gate wiring (2). An electrode layer (8) is provided on the insulating film (7) and the first and second front surface electrodes (3,4) across the gate wiring (2). A rear surface electrode (9) is provided on the rear surface of the semiconductor substrate (1). A first plated electrode (10) is provided on the electrode layer (8). A second plated electrode (11) is provided on the rear surface electrode (9).
Imaging module can easily and stably connect an imaging-sensing device to a coaxial cable
An imaging module of the invention includes: an image-sensing device that has a light-receiving face, a terminal surface located on an opposite side of the light-receiving face, and a plurality of image-sensing terminals provided on the terminal surface; a support that has a first end disposed on the terminal surface, a second end disposed on an opposite side of the first end, a side face disposed between the first end and the second end, and a guide disposed on the side face so as to correspond to positions of the image-sensing terminals and that is formed of an insulator; a coaxial cable including a conductor disposed on the guide; and solder that electrically connects the conductor to an image-sensing terminal corresponding to the conductor on the guide.
Electrical joint structure
An electrical joint structure including a substrate, a multi-layer bonding structure, and a blocking layer is provided. The multi-layer bonding structure is present on the substrate and includes a diffusive metal layer and a tin-rich layer. The diffusive metal layer includes a copper-tin alloy on a surface of the diffusive metal layer. The surface faces the substrate. A thickness of the copper-tin alloy is less than or equal to 2 m. The tin-rich layer is present on and in contact with the diffusive metal layer. The blocking layer is present between the multi-layer bonding structure and the substrate and at least in contact with a part of said copper-tin alloy, such that the multi-layer bonding structure is spaced apart from the substrate.
OPTICAL SEMICONDUCTOR ELEMENT
Provided is an optical semiconductor element in which an unbonded portion between an optical semiconductor chip and a submount is made small, heat dissipation efficiency becomes high, and service life can be made long. The optical semiconductor element can include: a submount; a submount electrode provided on a mounting surface of the submount and having a rectangular shape as a whole; and a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the submount electrode via a bonding layer. The chip electrode has a shape with chipped corners corresponding to four corners of the submount electrode, which has an exposed surface that is a portion exposed from the chip electrode at the four corners and bonded to the chip electrode to coincide with each other. The bonding layer extends to all the four corners of the exposed surface.
SEMICONDUCTOR DEVICE
The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.
IMAGING MODULE
An imaging module of the invention includes: an image-sensing device that has a light-receiving face, a terminal surface located on an opposite side of the light-receiving face, and a plurality of image-sensing terminals provided on the terminal surface; a support that has a first end disposed on the terminal surface, a second end disposed on an opposite side of the first end, a side face disposed between the first end and the second end, and a guide disposed on the side face so as to correspond to positions of the image-sensing terminals and that is formed of an insulator; a coaxial cable including a conductor disposed on the guide; and solder that electrically connects the conductor to an image-sensing terminal corresponding to the conductor on the guide.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor substrate (1) has a front surface and a rear surface facing each other. A gate wiring (2) and first and second front surface electrodes (3,4) are provided on the front surface of the semiconductor substrate (1). The first and second front surface electrodes (3,4) are separated from each other by the gate wiring (2). An insulating film (7) covers the gate wiring (2). An electrode layer (8) is provided on the insulating film (7) and the first and second front surface electrodes (3,4) across the gate wiring (2). A rear surface electrode (9) is provided on the rear surface of the semiconductor substrate (1). A first plated electrode (10) is provided on the electrode layer (8). A second plated electrode (11) is provided on the rear surface electrode (9).
Structure and formation method of chip package with protective lid
A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.