The semiconductor device according to the present disclosure has features (1) to (3) below. The feature (1) is that “a lower surface of an on-chip bonding material has a shape matching a surface shape of a main current wiring connection region in plan view”. The feature (2) is that “an emitter sense wiring is directly connected to a side surface of the main current wiring connection region”. The feature (3) is that “an IGBT chip has an ineffective region in which the IGBT does not function in a region below an emitter sense pad and the emitter sense wiring”.

An LED assembly includes an omnidirectional light field. The LED assembly has a transparent substrate with first and second surfaces facing to opposite orientations respectively. LED chips are mounted on the first surface and are electrically interconnected by a circuit. A transparent capsule with a phosphor dispersed therein is formed on the first surface and substantially encloses the circuit and the LED chips. First and second electrode plates are formed on the first or second surface, and electrically connected to the LED chips.

A lead frame is disclosed. In an embodiment, the lead frame includes a frame having a plurality of lead frame sections, wherein the lead frame sections are connected to the frame, wherein the frame has at least two longitudinal sides and at least two transverse sides, wherein at least in one longitudinal side includes an imprint, and wherein the imprint bolsters stability of the longitudinal side against sagging.

A glazing comprising a luminous means with a substrate having a first main surface, to which a first electrode is applied, a second electrode, and an organic layer stack within an active region of the substrate between the first and the second electrode, wherein the organic layer stack comprises at least one organic layer which is suitable for generating light, wherein the luminous means is arranged between two glass plates of the glazing of a window. Also, storage furniture is disclosed comprising a storage element shaped in planar fashion and having at least one storage surface and at least one radiation-emitting component, and at least one holding apparatus for holding the storage element.

A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and having relatively narrow edge surfaces and first and second relatively large face surfaces; at least one recess formed along an edge surface; a layer of a conducting material formed on a surface of each of the at least one recess; a first plurality of soldering pads on the first face surface configured to make electrical contact with a semiconductor device; and electrically conducting connections each of which electrically connects a soldering pad in the first plurality of soldering pads to the layer of conducting material of a recess of the at least one recess.

A semiconductor device includes a mounting substrate having a first surface, a semiconductor chip mounted on the first surface and having a second surface facing a side opposite to the first surface, and a wire extending from a first joint point on the first surface toward a second joint point on the second surface and electrically connecting the mounting substrate and the semiconductor chip to each other by connecting the first joint point and the second joint point to each other. The wire includes a first part, a first bent portion, a second part, a second bent portion, and a third part arranged in order from the first joint point toward the second joint point. The first part is positioned on the first surface side with respect to the second surface when viewed in a first direction along the first surface and the second surface.

Some embodiments relate to a bond pad structure of an integrated circuit (IC). In one embodiment the bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern.

A switch module (1) includes RF input/output wires (51a, 51c) connecting RF input/output pad electrodes (11a, 11c) and RF input/output lead electrodes (31a, 31c), control signal wires (52a, 52b) connecting control-signal pad electrodes (12a, 12b) and control-signal lead electrodes (32a, 32b), and a ground wire (53a) connected to a ground pad electrode (13a). The control-signal pad electrodes (12a, 12b), the control-signal lead electrodes (32a, 32b), and the control signal wires (52a, 52b) are disposed in a region (a2) on the opposite side, with respect to a boundary defined by a linear line (L1) along an extension direction of the ground wire (53a), to a region (a1) in which the RF input/output wire (51a), the RF input/output pad electrode (11a), and the RF input/output lead electrode (31a) are disposed.

A lead frame strip with corrugated saw street metal where the corrugated saw street metal is comprised of a partial thickness of the lead frame strip metal. A lead frame strip with corrugated saw street metal where the corrugated saw street metal is comprised of a half thickness of the lead frame strip metal.

The semiconductor device includes a semiconductor element, a plurality of terminal electrodes, internal wiring, and a sealing material. The semiconductor element is mounted on a circuit pattern provided on an insulating substrate. The plurality of terminal electrodes are provided on a case in which the insulating substrate and the semiconductor element are contained. The internal wiring connects the semiconductor element and the plurality of terminal electrodes. The sealing material fills a space in the case. The internal wiring includes a plurality of circuit patterns, a plurality of metal blocks, and metal wire. The plurality of metal blocks are electrically connected to the respective circuit patterns. The metal wire connects the plurality of metal blocks and is bonded to the plurality of metal blocks at positions closer to an upper surface of the sealing material than surfaces of the plurality of circuit patterns.