A semiconductor device improved in deterioration detection accuracy by using an inductance of a bonding wire. The semiconductor device includes a first conductor pattern formed on the insulating substrate, the main current of the semiconductor die device flowing through the first conductor pattern; a second conductor pattern formed on the insulating substrate for sensing the potential of the surface electrode of the semiconductor die device; a first bonding wire for connecting the surface electrode and the first conductor pattern; and a second bonding wire. Further, there is a voltage sensing unit which is connected to the first conductor pattern and the second conductor pattern to sense a potential difference between the first conductor pattern and the second conductor pattern at the time of switching of the semiconductor die device; and a deterioration detection unit for detecting deterioration of the first bonding wire by using the sensed potential difference.

[Problem] An object of the present invention is to miniaturize and integrate plural power semiconductors in an electronic circuit in a low cost without occurrence of a problem of a heat dissipation or the like.

[Means for solving the problem] The present invention is a power semiconductor module that comprises plural arrangements of power semiconductor elements comprising a power semiconductor bare chip which one electrode portion thereof is connected to a metal plate which at least one external connecting terminal is formed and other external connecting terminals which are electrically connected to other electrode portions of the power semiconductor bare chip, and that are contained in a same package, comprises wherein the power semiconductor elements are basically same outline, electrodes of the bare chip of the power semiconductor elements are mutually connected between the power semiconductor elements with a metal connector or a wiring, and the package is a resin mold package that seals the power semiconductor elements with an electrical insulating resin.

A switch module (1) includes RF input/output wires (51a, 51c) connecting RF input/output pad electrodes (11a, 11c) and RF input/output lead electrodes (31a, 31c), control signal wires (52a, 52b) connecting control-signal pad electrodes (12a, 12b) and control-signal lead electrodes (32a, 32b), and a ground wire (53a) connected to a ground pad electrode (13a). The control-signal pad electrodes (12a, 12b), the control-signal lead electrodes (32a, 32b), and the control signal wires (52a, 52b) are disposed in a region (a2) on the opposite side, with respect to a boundary defined by a linear line (L1) along an extension direction of the ground wire (53a), to a region (a1) in which the RF input/output wire (51a), the RF input/output pad electrode (11a), and the RF input/output lead electrode (31a) are disposed.

A semiconductor package includes at least one die attach pad of a leadframe, at least one semiconductor die mounted on the at least one die attach pad; and a plurality of lead terminals disposed around the at least one die attach pad and electrically connected to respective input/output (I/O) pads on the at least one semiconductor die through a plurality of bond wires. The plurality of lead terminals comprises first lead terminals, second lead terminals, and third lead terminals, which are arranged in triple row configuration along at least one side of the semiconductor package. Each of the first lead terminals, second lead terminals, and third lead terminals has an exposed base metal on a cut end thereof.

An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.