A semiconductor device is provided, which includes a semiconductor chip; a first current input/output portion that is electrically connected to the semiconductor chip; a second current input/output portion that is electrically connected to the semiconductor chip; three or more conducting portions provided with the semiconductor chip, between the first current input/output portion and the second current input/output portion; and a current path portion having a path through which current is conducted to each of the three or more conducting portions, wherein the current path portion includes a plurality of slits.

A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second transistors (e.g., main and peaking transistors) with first and second output terminals, respectively, all of which is integrally-formed with a semiconductor die. A signal path through the second transistor extends in a direction from a control terminal of the second transistor to the second output terminal, where the second output terminal corresponds to or is closely electrically coupled to a combining node. The amplifier also includes an integrated phase delay circuit that is configured to apply an overall phase delay (e.g., 90 degrees) to a signal carried between the first and second output terminals. The integrated phase delay circuit includes delay circuit wirebonds coupled between the first and second output terminals, and the delay circuit wirebonds extend in a third direction that is angularly offset from (e.g., perpendicular to) the second direction.

A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

A semiconductor device includes a first insulation member, a first drive conductive layer, a first semiconductor element, a second insulation member, a second drive conductive layer, a second semiconductor element, a connection member, and an encapsulation resin. The encapsulation resin encapsulates the first semiconductor element, the second semiconductor element, and the connection member. The connection member has a higher thermal conductivity than the encapsulation resin. The connection member forms a heat conduction path between the first insulation member and/or the first drive conductive layer and the second insulation member and/or the second drive conductive layer. The connection member has a higher thermal conductivity than the encapsulation resin.

A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.

The semiconductor module includes a first device that has an IGBT and a second device that has a reflux diode which is anti-parallel connected to the IGBT, which has a forward threshold voltage less than a reverse withstand voltage of the IGBT, and which has a forward breakdown voltage in excess of the reverse withstand voltage of the IGBT.

A semiconductor device includes a semiconductor chip and a package. The semiconductor chip includes a signal processing circuit, a plurality of pads, and a first resistor which arc formed on a semiconductor substrate. On the semiconductor chip, there is no shot-circuiting between a first pad and a second pad of the plurality of pads. A signal input terminal of the signal processing circuit is connected to the second pad. The first resistor is provided between a reference potential supply terminal for supplying a power supply potential and the first pad. A specific terminal of the plurality of terminals of the package is connected to the first pad by a first bonding wire, and is connected to the second pad by a second bonding wire.

A power module (1) includes a group of at least three rectangular electrical power components (11, 12, 13, 14, 23, 24, 25, 26) arranged on a substrate (2), wherein in that at least one side (31) of at least one of the rectangular electrical power components (11, 14) is not orthogonal or parallel to a line (3) that passes through the geometric centres of the remaining rectangular electrical power components (12, 13) of the group.

A semiconductor device includes a semiconductor element, a support member, and a bonding layer interposed between the semiconductor element and the support member, wherein the bonding layer contains an alloy of first metal and second metal.

A semiconductor device, including an insulated circuit substrate that has a base plate, a resin layer disposed on a front surface of the base plate, and a circuit pattern disposed on a front surface of the resin layer; and a semiconductor chip that is rectangular in a plan view of the semiconductor device and is bonded to a front surface of the circuit pattern in such a manner that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by at least a predetermined distance. Both the predetermined distance and a thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip.