A power module substrate 10 is provided with: an insulating substrate 1; and a metal sheet 2 that is joined to the insulating substrate 1 via a brazing material 3, wherein regarding the surface roughness, in the thickness direction, of the lateral surface of the metal sheet 2, the surface roughness of a corner 2a farthest from the center of the metal sheet 2 is larger than the surface roughness of plane parts 2b, which bound the corner, in at least a plan view. Also provided is a power module 100 which is formed by mounting an electronic component 40 on this power module substrate 10.

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.

A semiconductor device includes a semiconductor chip having an electrode pad, a terminal having a terminal pad, and a bonding wire. The bonding wire includes a first end portion, a first bonded portion bonded to the electrode pad, a loop portion extending between the semiconductor chip and the terminal, and a second bonded portion bonded to the terminal pad. The second bonded portion is a wedge bonded portion comprising a second end portion of the bonding wire opposite to the first end portion. A length of the first bonded portion in the first direction is greater than a length of the second bonded portion in the first direction.

A semiconductor device includes a semiconductor chip having an electrode pad, a terminal having a terminal pad, and a bonding wire. The bonding wire includes a first end portion, a first bonded portion bonded to the electrode pad, a loop portion extending between the semiconductor chip and the terminal, and a second bonded portion bonded to the terminal pad. The second bonded portion is a wedge bonded portion comprising a second end portion of the bonding wire opposite to the first end portion. A length of the first bonded portion in the first direction is greater than a length of the second bonded portion in the first direction.

A semiconductor package includes a pad and leads having a planar profile shaped from a planar base metal, a semiconductor die attached to the pad, a wire bond extending from the semiconductor die to a respective lead, and mold compound covering the semiconductor die, the wire bond, and a first portion of the respective lead, wherein a second portion of the respective lead extends beyond the mold compound. A shape of the respective lead within the planar profile includes a notch indented relative to a first elongated side of the shape of the respective lead and a protrusion protruding outwardly relative to a second elongated side of the shape of the respective lead. The notch and the protrusion are each partially covered by the mold compound and partially outside the mold compound.

A semiconductor package includes a pad and leads having a planar profile shaped from a planar base metal, a semiconductor die attached to the pad, a wire bond extending from the semiconductor die to a respective lead, and mold compound covering the semiconductor die, the wire bond, and a first portion of the respective lead, wherein a second portion of the respective lead extends beyond the mold compound. A shape of the respective lead within the planar profile includes a notch indented relative to a first elongated side of the shape of the respective lead and a protrusion protruding outwardly relative to a second elongated side of the shape of the respective lead. The notch and the protrusion are each partially covered by the mold compound and partially outside the mold compound.