In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

The method for shuffled decoding of LDPC codes includes calculating check-variable mutual information which is mutual information of a message propagating from a plurality of check nodes to a plurality of variable nodes by a check-variable mutual information calculating unit, calculating variable-check mutual information which is mutual information of a message propagating from the plurality of variable nodes to the plurality of check nodes connected to the plurality of variable nodes based on the check-variable mutual information by a variable-check mutual information calculating unit, and Calculating the entire mutual information which is a sum of variable-check mutual information for each of the plurality of variable nodes and determines an operation order of a variable node having the largest entire mutual information among the plurality of variable nodes to be next, by an operation order determining unit.

In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

A decoding system for an iterative decoding of a parity check code comprises a first loop circuit adapted to store log-likelihood ratio values corresponding to a plurality of received data symbols in a memory unit; a second loop circuit adapted to compute a difference between a check-to-variable log-likelihood message at a second iteration step, and a check-to-variable log-likelihood message at a first iteration step, when the first iteration step precedes the second iteration step; and an adder unit adapted to update a log-likelihood ratio value stored on the first loop circuit by adding the difference computed in the second loop circuit; wherein the first loop circuit and the second loop circuit are synchronized such that the adder unit forwards the updated log-likelihood ratio value synchronously both to the first loop circuit and to the second loop circuit.

An apparatus for receiving a signal. The apparatus may include a demodulator configured to generate a binary signal from a received signal, a clock data recovery (CDR) circuitry configured to detect a phase error of the binary signal and generate CDR state information for the binary signal, a soft information generation circuitry configured to map the CDR state information to soft information for the binary signal, and a decoder configured to decode the binary signal using the soft information. The CDR circuitry may generate the CDR state information from multiple consecutive samples of the binary signal at least twice a symbol rate of the received signal. The soft information may be a log likelihood ratio of the binary signal, and the soft information generation circuitry may determine the log likelihood ratio based on an input bit error rate of the binary signal.

Various method and apparatus embodiments for data dependent error correction code (ECC) encoding are disclosed. In one embodiment, a data object may include multiple portions, with each portion having different characteristics. An ECC encoder may allocate error correction resources (e.g., parity bits) to the different portions at respectively different data rates (e.g., more error correction resources to some portions relative to other portions). Upon completion of the allocation, the data object and the associated error correction resources are forwarded to a storage medium for storage therein.

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives d.sub.c input lists U.sub.i and delivers and delivers d.sub.c output lists V.sub.i, with i[1 . . . d.sub.c]. Each input list and output list includes n.sub.m elements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q>n.sub.m. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of d.sub.c elements of input lists U.sub.i. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list.

A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

An encoding method, a decoding method, an electronic device and a storage medium are disclosed. The encoding method includes: acquiring stored data in a storage system, and acquiring nodes corresponding to the stored data to obtain a number of the nodes; dividing the acquired stored data into a sequence of information vectors, and generating an information matrix according to the number of the nodes and a number of the sequence of information vectors; and calculating an encoded block according to each information vector and the information matrix to obtain a sequence of encoded blocks.