A coded signal is received via a physical channel. The coded signal is encoded by a parity check matrix. In some examples, the coded signal is low density parity check-encoded. The coded signal is decoded to determine a result signal. Said decoding alternatingly updates, for each one of a number of iterations, bit node values representing bits of the result signal and check node values representing constrains of the parity check matrix. In some examples, the decoding determines the result signal at a first precision and updates at least partly at a second precision which is lower than the first precision. In further examples, the number of iterations is dynamically adjusted.

A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Low-density parity-check (LDPC) encoded data with one or more errors is received. Information associated with an early convergence checkpoint that occurs at a fractional iteration count that is strictly greater than 0 and strictly less than 1 is received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, wherein the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. At the early convergence checkpoint that occurs at the fractional iteration count, it is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

Embodiments of the invention provide a check node processing unit implemented in a decoder, said decoder being configured to decode a signal encoded using an error correcting code, said signal comprising symbols, the check node processing unit being configured to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components, each component comprising a value of a symbol and a reliability metrics associated with said symbol, wherein the check node processing unit comprises: a data structure (31) configured to store said input messages, the components of the input messages being associated with an integer index in the data structure; a data processing unit (33) configured to apply one or more iterations of a transformation operation to at least a part of the data structure, each iteration of the transformation operation being performed to arrange the components of said input messages in said data structure (31) depending on at least some of the components of the messages associated with a given value of the integer index, which provides a transformed data structure; a calculation unit (35) configured to determine said at least one output message from the components comprised in said transformed data structure.

Embodiments of the present disclosure relate to a device, a method, an apparatus and a computer readable storage medium for data processing. In example embodiments, a method of data processing is provided. The method comprises obtaining, from a channel decoding process, a first input and a second input on which a sum-product operation is to be performed, the sum-product operation including one or more sub-operations. The method further comprises determining a set of mapping relationships for approximating at least one of the one or more sub-operations. The method further comprises determining, based on the first input, the second input and the set of mapping relationships, a first result of the sum-product operation, and continuing the channel decoding process based on the first result. As such, embodiments of the present disclosure can improve error correcting capabilities of Low Density Parity Check (LDPC) code, Polar code, Reed-Muller (RM) code or the like.

A controller is configured to access information to generate data blocks. The controller includes a data block interleaver and a low-density parity check (LDPC) decoder. The data block interleaver is configured to interleave the data blocks to generate interleaved data blocks. The LDPC decoder is configured to decode the interleaved data blocks.

A method for decoding a low-density parity-check (LDPC) code, performed by a communication apparatus, includes: updating a variable node; determining n minimum values based on a min-sum algorithm (MSA); determining n indices based on the n minimum values; updating a check node using the n indices; calculating a log-likelihood ratio (LLR) value when the update of the check node is completed; and determining an information bit based on the LLR value.

A saturation metric that represents a degree of saturation in a low-density parity-check (LDPC) decoding system that uses a fixed-point number representation is determined. The saturation metric is compared against a saturation threshold. In the event the saturation metric exceeds the saturation threshold, at the end of a decoding iteration, a message is more aggressively attenuated compared to when the saturation metric does not exceed the saturation threshold in order to produce an attenuated message. In the event the saturation metric does not exceed the saturation threshold, at the end of the decoding iteration, the message is less aggressively attenuated compared to when the saturation metric does exceed the saturation threshold in order to produce the attenuated message.

The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method of a receiving apparatus in a communication system supporting a low density parity check (LDPC) code is provided. The method includes deactivating variable nodes of which absolute values of log likelihood ratio (LLR) values are greater than or equal to a first threshold value; changing LLR values of variable nodes of which absolute values of LLR values are less than a second threshold value among variable nodes other than the deactivated variable nodes to a preset value, and detecting LLR values of check nodes based on LLR values of the variable nodes other than the deactivated variable nodes.

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword has bits from defective bit locations and non-defective bit locations. A syndrome of a current copy of the codeword is determined. Channel information for non-defective bit locations is determined using the current copy of the codeword and the received codeword from the memory device. Energy function values are determined for bits of the codeword using the syndrome of the current copy. Determining the energy function values includes using the channel information for bits in non-defective bit locations and omitting channel information for bits in defective bit locations. One or more bits of the codeword are flipped in response to the energy function values for the one or more bits satisfying a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.