The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

Devices, systems, and methods for dynamic control of a quasi-cyclic low-density parity-check (QC-LDPC) bit-flipping decoder are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from an irregular QC-LDPC code, performing a plurality of decoding iterations on the received noisy codeword, each of the plurality of decoding iterations comprising processing of N circulant matrices, performing, before processing a current circulant matrix in a current M-th iteration of the plurality of decoding iterations, operations that include computing a number of bit flips that have occurred over the processing of N previous circulant matrices, the N previous circulant matrices spanning the current M-th iteration and an (M−1)-th iteration, wherein M and N are positive integers, and wherein M≥2, and updating, based on the number of bit flips, a bit-flipping threshold, and processing, based on the updated bit-flipping threshold, the current circulant matrix.

A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.

Provided are a decoding method, a decoding device and a decoder. The method includes: setting a decoder parallelism P, and splitting soft information of a block to be decoded according to the parallelism P; performing decoding calculation on the block to be decoded according to the split information, and outputting decoded hard bit information; and recombining the hard bit information according to the parallelism P.

Examples relate to a decoding apparatus, a decoding device, a decoding method, a decoding computer program, and a communication device, a memory device and a storage device comprising such a decoding apparatus or decoding method. A decoding apparatus for performing iterative decoding on a codeword comprises processing circuitry comprising a plurality of processing units, and control circuitry configured to control the iterative decoding of the codeword. The iterative decoding is based on a parity-check matrix. The matrix is sub-divided into two or more partitions. The control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length. The control circuitry is configured to multiplex the utilization of the plurality of processing units across the two or more partitions of the matrix at least in the second mode of operation.

A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.

A method for channel encoding in a communication or broadcasting system is provided. The method includes determining a block size Z, and performing encoding based on the block size and a first matrix corresponding to the block size, wherein the first matrix is determined based on information and a plurality of second matrices, and wherein a part of a column index indicating a position of a non-zero element in each row of the information includes an index according to mathematical expression 22 above.

Provided is an information processing method. The method includes that: first data to be decoded and one or more decoding parameters of the first data are obtained; a basis matrix is determined based on the one or more decoding parameters; a decoding instruction set including a plurality of decoding instructions is determined based on the basis matrix, wherein the plurality of decoding instructions include elements in the basis matrix; and the first data is decoded based on the decoding instruction set. Further provided are an information processing device and a computer storage medium.

Embodiments herein relate to e.g., a method performed by a network node for handling a received signal in a communication network. The network node includes at least two processing cores connected via a bus system for handling the received signal. The network node receives input bits associated with the received signal and permutes the received input bits into input bits of permuted order taking at least number of processing cores into account. The network node further decodes the input bits of the permuted order and re-permutes the decoded input bits into original order.

Provided are a decoding method, a decoding device and a decoder. The method includes: setting a decoder parallelism P, and splitting soft information of a block to be decoded according to the parallelism P; performing decoding calculation on the block to be decoded according to the split information, and outputting decoded hard bit information; and recombining the hard bit information according to the parallelism P.