Disclosed are devices, systems and methods for error correction encoding and decoding. A memory controller includes an error correction encoder for generating a codeword by performing error correction encoding, using a parity check matrix including a plurality of sub-matrices; and an error correction decoder for performing error correction decoding on a read vector corresponding to the codeword on a column layer basis while sequentially selecting column layers of the parity check matrix used for the error correction encoding, in the error correction decoding, the column layer including a set of columns of the parity check matrix. Rows included in the parity check matrix are grouped into a plurality of row groups, and at most one cyclic permutation matrix (CPM) is included for each column layer in each of the row groups.

A device is disclosed. The device may include an input buffer to receive a first low bit width message. A reconstruction circuit may implement a reconstruction function on the first low bit width message, producing a first high bit width message. A computation circuit may implementing a computation function on the first high bit width message, producing a second high bit width message. A quantization circuit may implementing a quantization function on the second high bit width message, producing a second low bit width message. A decision buffer may then store the second low bit width message. The reconstruction function and the quantization function may vary depending on an iteration and a layer of the device.

A hardware efficient implementation of a threshold modified attenuated min-sum algorithm (TAMSA”) and a threshold modified offset min-sum algorithm (“TOMSA”) that improve the performance of a low density parity-check (“LDPC”) decoder by reducing the bit error rate (“BER”) compared to the conventional attenuated min-sum algorithm (“AMSA”), offset min-sum algorithm (“OMSA”), and the min-sum algorithm (“MSA”). Embodiments of the present invention preferably use circuit optimization techniques, including a parallel computing structure and lookup tables, and a field-programmable gate array (“FPGA”) or application specific integrated circuit (“ASIC”) implementation.

A method of optimizing an iterative process defines a set of trainable parameters and a differentiable gating function to be applied to each parameter in the set of trainable parameters. A trainable model of the iterative process is built, wherein the iterative process is modified by using the value of the differentiable gating function applied to the parameters to compute a weighted sum of internal variables of the iterative process before and after each iteration. A machine learning-based optimization of the trainable model of the iterative process determines a subset of iterations of the iterative process to perform. The subset of iterations is determined such that an accuracy and a number of active iterations of the iterative process are jointly optimized. The method processes only the subset of the iterations to perform the iterative process. The method is applied to optimize the layered belief propagation algorithm for LDPC decoding.

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.

In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block and a multidimensional inverse FFT processing block that process the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop. The communication system can be bandwidth constrained, and the signal can comprise an information rate that is higher than that of a communication system without intentional introduction of the memory at the transmitter.

Disclosed herein is a decoder 10 for decoding a family of L rate compatible parity check codes, said family of parity check codes comprising a first code that can be represented by a bipartite graph having variable nodes, check nodes, and edges, and L−1 codes of increasingly lower code rate, among which the i-th code can be represented by a bipartite graph corresponding to the bipartite graph representing the (i−1)-th code, to which an equal number of n.sub.i variable nodes and check nodes are added, wherein the added check nodes are connected via edges with selected ones of the variable nodes included in said i-th code, while the added variable nodes are connected via edges with selected added check nodes only. The decoder comprising L check node processing units 14, among which the i-th check node processing unit processes only the check nodes added in the i-th code over the (i−1)-th code, wherein said L check node processing units 14 are configured to operate in parallel.

The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.

An operating method of a low density parity check (LDPC) decoder, the operating method includes: initially updating codewords to variable nodes; determining an update order in which a plurality of variable node groups are updated, which is determined based on reliability of each of the variable node groups; executing local iterations including update of check nodes associated with a select variable node group among the variable node groups and update of the select variable node group based on the updated check nodes until all the variable node groups are updated based on the update order; performing syndrome check to determine whether LDPC decoding is successful, based on an operation of the updated variable nodes and a parity check matrix.