The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

A sorting device for determining elementary check node components in an elementary check node processor (3) implemented in a non-binary error correcting code decoder by sorting auxiliary components. The auxiliary components are stored in a plurality of FIFO memories (33-n), each FIFO memory (33-n) being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory (33-n) comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory (33-n). The sorting device is configured to sort the auxiliary components by a plurality of multiplexers (34-m) arranged sequentially. Each multiplexers (34-m) is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the following steps: receive an auxiliary component extracted from the FIFO memory (33-n) which is assigned the FIFO number index comprised in the candidate elementary check node component determined at the previous iteration which comprises the most reliable candidate symbol, and update the candidate elementary check node component determined at the previous iteration by selecting one component among the received auxiliary component, the candidate elementary check node component determined at the previous iteration by the multiplexer (34-m), and the candidate elementary check node component determined at the previous iteration by the subsequent multiplexer (34-(m+1)).

The sorting device is configured to determine, at each of the one or more iterations, an elementary check node component by selecting the candidate elementary check node component which comprises the most reliable candidate symbol.

Methods and devices for encoding source words and decoding codewords wherein encoding a source word includes: receiving a 1×K source word row vector ū; and generating a 1×N codeword vector c=ū.Math.G, wherein G is a K×N generator matrix derived from a parity check matrix H.sub.I; and wherein the parity check matrix H.sub.I is derived from a base parity check matrix H by applying an optimized lifting matrix to the base parity check matrix H.

Memory controllers, decoders and methods to perform decoding of user bits and parity bits including those corresponding to low degree variable nodes. For each of the user bits, the decoder performs a variable node update operation and a check node update operation for connected check nodes. After all of the user bits are processed, the decoder performs a parity node update operation for the parity bits using results of the variable node and check node update operations performed on the user bits.

A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention comprises: a step of generating a multi-edge LDPC code matrix which comprises a high rate code matrix and a single parity check code matrix; and a step of encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix may be configured by connecting a first matrix which is configured as a quasi row-orthogonal structure matrix and a second matrix which is configured as a pure row-orthogonal structure.

This application discloses an LDPC code-based decoding method and apparatus, and pertains to the field of communications technologies. In this application, n×L LLR values may be decoded based on a target element in a target basis matrix, and a non-target element in the target basis matrix is forbidden to participate in decoding the n×L LLR values. The non-target element is a zero matrix, and the LLR value does not change after the LLR value is processed based on the non-target element. Therefore, the non-target element in the target basis matrix is forbidden to participate in decoding. In this way, decoding of the LLR value is not affected. In addition, a decoding time overhead and an occupied resource are reduced and decoding performance is improved because the LLR value is no longer processed based on a non-target element.

An operating method of a low density parity check (LDPC) decoder, the operating method includes: initially updating codewords to variable nodes; determining an update order in which a plurality of variable node groups are updated, which is determined based on reliability of each of the variable node groups; executing local iterations including update of check nodes associated with a select variable node group among the variable node groups and update of the select variable node group based on the updated check nodes until all the variable node groups are updated based on the update order; performing syndrome check to determine whether LDPC decoding is successful, based on an operation of the updated variable nodes and a parity check matrix.

Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.

A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.

The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block and a multidimensional inverse FFT processing block that process the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop. The communication system can be bandwidth constrained, and the signal can comprise an information rate that is higher than that of a communication system without intentional introduction of the memory at the transmitter.